intr.c

WM9713 audio codec driver for WinCE 5.0

/*-----------------------------------------------------------------------------
 * Copyright (c) Wolfson Microelectronics plc.  All rights reserved.
 *
 * This software as well as any related documentation is furnished under 
 * license and may only be used or copied in accordance with the terms of the 
 * license. The information in this file is furnished for informational use 
 * only, is subject to change without notice, and should not be construed as 
 * a commitment by Wolfson Microelectronics plc. Wolfson Microelectronics plc
 * assumes no responsibility or liability for any errors or inaccuracies that
 * may appear in this document or any software that may be provided in
 * association with this document. 
 *
 * Except as permitted by such license, no part of this document may be 
 * reproduced, stored in a retrieval system, or transmitted in any form or by 
 * any means without the express written consent of Wolfson Microelectronics plc. 
 *
 * $Id: intr.c 1466 2005-03-23 10:05:29Z fb $
 *
 * MainstoneII board specific interrupt code.
 *
 * Warning:
 *  This driver is specifically written for Wolfson Codecs. It is not a 
 *  general CODEC device driver.
 *
 * --------------------------------------------------------------------------*/

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  File:  intr.h
//
//  This file contains MainstoneII board specific interrupt code.
//
#include <bsp.h>

#include "WMConfig.h"
#include "WMPlatform_Raw.h"

#define INTMSK_RESERVED_BITS          0xFFFF1100
#define INTSETCLR_RESERVED_BITS       0xFFFF1100

#define IRQ_GPIO0_PCMCIA_S1           (IRQ_BULVERDE_MAX + 16)  // 47
#define IRQ_GPIO0_PCMCIA_S1_CSC       (IRQ_BULVERDE_MAX + 15)  // 46
#define IRQ_GPIO0_PCMCIA_S1_CD        (IRQ_BULVERDE_MAX + 14)  // 45
#define IRQ_GPIO0_RSVD2               (IRQ_BULVERDE_MAX + 13)  // 44  ** RESERVED **
#define IRQ_GPIO0_PCMCIA_S0           (IRQ_BULVERDE_MAX + 12)  // 43
#define IRQ_GPIO0_PCMCIA_S0_CSC       (IRQ_BULVERDE_MAX + 11)  // 42
#define IRQ_GPIO0_PCMCIA_S0_CD        (IRQ_BULVERDE_MAX + 10)  // 41
#define IRQ_GPIO0_RSVD1               (IRQ_BULVERDE_MAX + 9)   // 40  ** RESERVED **
#define IRQ_GPIO0_EXPBD               (IRQ_BULVERDE_MAX + 8)   // 39
#define IRQ_GPIO0_MSINS               (IRQ_BULVERDE_MAX + 7)   // 38
#define IRQ_GPIO0_PENIRQ              (IRQ_BULVERDE_MAX + 6)   // 37
#define IRQ_GPIO0_AC97IRQ             (IRQ_BULVERDE_MAX + 5)   // 36
#define IRQ_GPIO0_ETHERNET            (IRQ_BULVERDE_MAX + 4)   // 35
#define IRQ_GPIO0_USBCD               (IRQ_BULVERDE_MAX + 3)   // 34
#define IRQ_GPIO0_USIMCD              (IRQ_BULVERDE_MAX + 2)   // 33
#define IRQ_GPIO0_MMCCD               (IRQ_BULVERDE_MAX + 1)   // 32

#define IRQ_GPIOXX_2_PEN_DETECT		  PEN_DETECT_GPIO_NUM

#define IRQ_MAINSTONEII_GPIO0_MIN     IRQ_GPIO0_MMCCD
#define IRQ_MAINSTONEII_GPIO0_MAX     IRQ_GPIO0_PCMCIA_S1

#define FPGA_INT_BIT(n)              (1 << (n - IRQ_MAINSTONEII_GPIO0_MIN))

static UINT32 FPGAInterruptHandler(UINT32 ra);
static UINT32 GPIOInterruptHandler(UINT32 ra);

static volatile MAINSTONEII_BLR_REGS *g_pBLRegs = NULL;
static volatile BULVERDE_GPIO_REG    *g_pGPIORegs = NULL;

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrInit
//
BOOL BSPIntrInit()
{
    volatile BULVERDE_INTR_REG *pIntrRegs = NULL;

    OALMSG(OAL_INTR&&OAL_FUNC, (L"+BSPIntrInit\r\n"));

    pIntrRegs   = (volatile BULVERDE_INTR_REG *) OALPAtoVA(BULVERDE_BASE_REG_PA_INTC, FALSE);
    g_pBLRegs   = (volatile MAINSTONEII_BLR_REGS *) OALPAtoVA(MAINSTONEII_BASE_REG_PA_FPGA, FALSE);
    g_pGPIORegs = (volatile BULVERDE_GPIO_REG *) OALPAtoVA(BULVERDE_BASE_REG_PA_GPIO, FALSE);

    // Mask and clear all FPGA interrupts.
    //
    g_pBLRegs->int_msk_en  = 0;
    g_pBLRegs->int_set_clr = 0;

    // Enable USB Cable detection interrupts
    OUTREG32((PULONG)&g_pBLRegs->int_msk_en, FPGA_INT_BIT(IRQ_GPIO0_USBCD));

    // Enable GPIO 0 for falling edge (Active Low) to signal the FPGA interrupts.
    //
    SETREG32((PULONG)&g_pGPIORegs->GFER0, XLLP_GPIO_BIT_0);
    SETREG32((PULONG)&pIntrRegs->icmr, (1 << IRQ_GPIO0));

    // Set up static interrupt mappings
    OALIntrStaticTranslate(SYSINTR_OHCI, IRQ_USBOHCI);
#if WM_MAINSTONEII_FPGA_PEN_DETECT
#if PENIRQ
    OALIntrStaticTranslate(SYSINTR_TOUCH, IRQ_GPIO0_PENIRQ);
#elif AC97IRQ
    OALIntrStaticTranslate(SYSINTR_TOUCH, IRQ_GPIO0_AC97IRQ);
#else
#	error Please define either AC97IRQ or PENIRQ
#endif
#else 
	OALIntrStaticTranslate(SYSINTR_TOUCH, IRQ_GPIOXX_2_PEN_DETECT);
#endif
    OALIntrStaticTranslate(SYSINTR_TOUCH_CHANGED, IRQ_OSMR1);
    OALIntrStaticTranslate(SYSINTR_KEYPAD, IRQ_KEYPAD);

    OALIntrStaticTranslate(SYSINTR_FFUART, IRQ_FFUART);
    OALIntrStaticTranslate(SYSINTR_BFUART, IRQ_BTUART);
    OALIntrStaticTranslate(SYSINTR_SFUART, IRQ_STUART);

    OALIntrStaticTranslate(SYSINTR_PCCARD_CSC_S0, IRQ_GPIO0_PCMCIA_S0_CSC);
    OALIntrStaticTranslate(SYSINTR_PCCARD_CD_S0, IRQ_GPIO0_PCMCIA_S0_CD);
    OALIntrStaticTranslate(SYSINTR_PCCARD_CSC_S1, IRQ_GPIO0_PCMCIA_S1_CSC);
    OALIntrStaticTranslate(SYSINTR_PCCARD_CD_S1, IRQ_GPIO0_PCMCIA_S1_CD);

    OALIntrStaticTranslate(SYSINTR_AUDIO, IRQ_DMAC);

    OALIntrStaticTranslate(SYSINTR_USBFN, IRQ_USBFN);

    OALMSG(OAL_INTR&&OAL_FUNC, (L"-BSPIntrInit\r\n"));

    return TRUE;
}

//------------------------------------------------------------------------------

BOOL BSPIntrRequestIrqs(DEVICE_LOCATION *pDevLoc, UINT32 *pCount, UINT32 *pIrqs)
{
    BOOL rc = FALSE;

    OALMSG(OAL_INTR&&OAL_FUNC, (
        L"+BSPIntrRequestIrq(0x%08x->%d/%d/0x%08x/%d, 0x%08x, 0x%08x)\r\n", 
        pDevLoc, pDevLoc->IfcType, pDevLoc->BusNumber, pDevLoc->LogicalLoc,
        pDevLoc->Pin, pCount, pIrqs
    ));

    // Check for input params
    if (pIrqs == NULL || pCount == NULL || *pCount < 1) goto Done;

    switch (pDevLoc->IfcType) {
    case Internal:
        switch ((ULONG)pDevLoc->LogicalLoc) {
        case (MAINSTONEII_BASE_REG_PA_SMSC_ETHERNET + 0x300):
            pIrqs[0] = IRQ_GPIO0_ETHERNET;
            *pCount = 1;
            rc = TRUE;
            break;
        }
        break;
    }

Done:
    OALMSG(OAL_INTR&&OAL_FUNC, (L"-BSPIntrRequestIrq(rc = %d)\r\n", rc));
    return rc;
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrEnableIrq
//
//  This function is called from OALIntrEnableIrq to enable interrupt on
//  secondary interrupt controller or GPIO controller.
//
UINT32 BSPIntrEnableIrq(UINT32 irq)
{
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrEnableIrq(%d)\r\n", irq));

    // Valid board-level interrupt?
    if (g_pBLRegs && (irq >= IRQ_MAINSTONEII_GPIO0_MIN) && (irq <= IRQ_MAINSTONEII_GPIO0_MAX))
    {
        UINT32 TempVal = (INREG32((PULONG)&g_pBLRegs->int_msk_en) & ~INTMSK_RESERVED_BITS);

        OUTREG32((PULONG)&g_pBLRegs->int_msk_en, (TempVal | FPGA_INT_BIT(irq)));

        // Enabling the interrupt at the FPGA controller is enough - no need to enable the Bulverde GPIO0 interrupt.
        irq = OAL_INTR_IRQ_UNDEFINED;
    }

#if !WM_MAINSTONEII_FPGA_PEN_DETECT
    /*
     * Enable the pen detect interrupt.
     */
	if ( g_pGPIORegs && ( IRQ_GPIOXX_2_PEN_DETECT == irq ) )
	{
		g_pGPIORegs->PEN_DETECT_GPIO_REG(GRER) |= GPIO_BIT(PEN_DETECT_GPIO_NUM);
	}
#endif

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrEnableIrq(irq = %d)\r\n", irq));
    return irq;
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrDisableIrq
//
//  This function is called from OALIntrDisableIrq to disable interrupt on
//  secondary interrupt controller or GPIO controller.
//
UINT32 BSPIntrDisableIrq(UINT32 irq)
{
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDisableIrq(%d)\r\n", irq));