📄 jb8-eqs.h
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* Copyright (c) Motorola 1999 *
* File Name: JB8-EQS.H *
* *
* Description: HC908JB8 Part Specific Framework *
* *
* *
* Assembler: CASM08Z (P&E Microcomputer Systems Inc) *
* Version: 3.16 *
* *
* Current Revision: 1.1 *
* Current Revision Release Date: 1999.12.07 by Derek Lau *
* *
* Updated History *
* Rev YYYY.MM.DD Author Description of Change *
* --- ----------- ------ --------------------- *
* 1.0 1999.04.13 Whitacre Original Release *
* 1.1 1999.12.07 Derek Lau Added more registers bits *
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* This Program is a freeware to demonstrate the operation of Motorola *
* Microcontroller. Motorola reserves the right to make changes without *
* further notice to any product herein to improve reliability, function, or *
* design. Motorola does not assume any liability arising out of the *
* application or use of any product, circuit, or software described herein; *
* neither does it convey any license under its patent rights nor the rights *
* of others. Motorola products are not designed, intended, or authorized *
* for use as components in systems intended for surgical implant into the *
* body, or other applications intended to support life, or for any other *
* application in which the failure of the Motorola product could create a *
* situation where personal injury or death may occur. Should Buyer purchase *
* or use Motorola products for any such intended or unauthorized *
* application, Buyer shall indemnify and hold Motorola and its officers, *
* employees, subsidiaries, affiliates, and distributors harmless against *
* all claims, costs, damages, and expenses, and reasonable attorney fees *
* arising out of, directly or indirectly, any claim of personal injury or *
* death associated with such unintended or unauthorized use, even if such *
* claim alleges that Motorola was negligent regarding the design or *
* manufacture of the part. Motorola and the Motorola logo* are registered *
* trademarks of Motorola Inc *
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; *
; Register Equates *
; *
;*****************************************************************************
*************************************************************
* PORT I/O
*************************************************************
PTA EQU $00 ;I/O PORT A
b_PTA7: EQU 7 ;PTA7 Input/Output Value
b_PTA6: EQU 6 ;PTA6 Input/Output Value
b_PTA5: EQU 5 ;PTA5 Input/Output Value
b_PTA4: EQU 4 ;PTA4 Input/Output Value
b_PTA3: EQU 3 ;PTA3 Input/Output Value
b_PTA2: EQU 2 ;PTA2 Input/Output Value
b_PTA1: EQU 1 ;PTA1 Input/Output Value
b_PTA0: EQU 0 ;PTA0 Input/Output Value
b_PTA7.: EQU %10000000 ;PTA7 Input/Output Value
b_PTA6.: EQU %01000000 ;PTA6 Input/Output Value
b_PTA5.: EQU %00100000 ;PTA5 Input/Output Value
b_PTA4.: EQU %00010000 ;PTA4 Input/Output Value
b_PTA3.: EQU %00001000 ;PTA3 Input/Output Value
b_PTA2.: EQU %00000100 ;PTA2 Input/Output Value
b_PTA1.: EQU %00000010 ;PTA1 Input/Output Value
b_PTA0.: EQU %00000001 ;PTA0 Input/Output Value
PTB EQU $01 ;I/O PORT B
b_PTB7 EQU 7 ;PTB7 Input/Output Value
b_PTB6 EQU 6 ;PTB6 Input/Output Value
b_PTB5 EQU 5 ;PTB5 Input/Output Value
b_PTB4 EQU 4 ;PTB4 Input/Output Value
b_PTB3 EQU 3 ;PTB3 Input/Output Value
b_PTB2 EQU 2 ;PTB2 Input/Output Value
b_PTB1 EQU 1 ;PTB1 Input/Output Value
b_PTB0 EQU 0 ;PTB0 Input/Output Value
b_PTB7. EQU %10000000 ;PTB7 Input/Output Value
b_PTB6. EQU %01000000 ;PTB6 Input/Output Value
b_PTB5. EQU %00100000 ;PTB5 Input/Output Value
b_PTB4. EQU %00010000 ;PTB4 Input/Output Value
b_PTB3. EQU %00001000 ;PTB3 Input/Output Value
b_PTB2. EQU %00000100 ;PTB2 Input/Output Value
b_PTB1. EQU %00000010 ;PTB1 Input/Output Value
b_PTB0. EQU %00000001 ;PTB0 Input/Output Value
PTC EQU $02 ;I/O PORT C
b_PTC7 EQU 7 ;PTC7 Input/Output Value
b_PTC6 EQU 6 ;PTC6 Input/Output Value
b_PTC5 EQU 5 ;PTC5 Input/Output Value
b_PTC4 EQU 4 ;PTC4 Input/Output Value
b_PTC3 EQU 3 ;PTC3 Input/Output Value
b_PTC2 EQU 2 ;PTC2 Input/Output Value
b_PTC1 EQU 1 ;PTC1 Input/Output Value
b_PTC0 EQU 0 ;PTC0 Input/Output Value
b_PTC7. EQU %10000000 ;PTC7 Input/Output Value
b_PTC6. EQU %01000000 ;PTC6 Input/Output Value
b_PTC5. EQU %00100000 ;PTC5 Input/Output Value
b_PTC4. EQU %00010000 ;PTC4 Input/Output Value
b_PTC3. EQU %00001000 ;PTC3 Input/Output Value
b_PTC2. EQU %00000100 ;PTC2 Input/Output Value
b_PTC1. EQU %00000010 ;PTC1 Input/Output Value
b_PTC0. EQU %00000001 ;PTC0 Input/Output Value
PTD EQU $03 ;I/O PORT D
b_PTD7 EQU 7 ;PTD7 Input/Output Value
b_PTD6 EQU 6 ;PTD6 Input/Output Value
b_PTD5 EQU 5 ;PTD5 Input/Output Value
b_PTD4 EQU 4 ;PTD4 Input/Output Value
b_PTD3 EQU 3 ;PTD3 Input/Output Value
b_PTD2 EQU 2 ;PTD2 Input/Output Value
b_PTD1 EQU 1 ;PTD1 Input/Output Value
b_PTD0 EQU 0 ;PTD0 Input/Output Value
b_PTD7. EQU %10000000 ;PTD7 Input/Output Value
b_PTD6. EQU %01000000 ;PTD6 Input/Output Value
b_PTD5. EQU %00100000 ;PTD5 Input/Output Value
b_PTD4. EQU %00010000 ;PTD4 Input/Output Value
b_PTD3. EQU %00001000 ;PTD3 Input/Output Value
b_PTD2. EQU %00000100 ;PTD2 Input/Output Value
b_PTD1. EQU %00000010 ;PTD1 Input/Output Value
b_PTD0. EQU %00000001 ;PTD0 Input/Output Value
DDRA EQU $04 ;Port A Data Direction
b_DDRA7 EQU 7 ;PTA7 Data Direction
b_DDRA6 EQU 6 ;PTA6 Data Direction
b_DDRA5 EQU 5 ;PTA5 Data Direction
b_DDRA4 EQU 4 ;PTA4 Data Direction
b_DDRA3 EQU 3 ;PTA3 Data Direction
b_DDRA2 EQU 2 ;PTA2 Data Direction
b_DDRA1 EQU 1 ;PTA1 Data Direction
b_DDRA0 EQU 0 ;PTA0 Data Direction
b_DDRA7. EQU %10000000 ;PTA7 Data Direction
b_DDRA6. EQU %01000000 ;PTA6 Data Direction
b_DDRA5. EQU %00100000 ;PTA5 Data Direction
b_DDRA4. EQU %00010000 ;PTA4 Data Direction
b_DDRA3. EQU %00001000 ;PTA3 Data Direction
b_DDRA2. EQU %00000100 ;PTA2 Data Direction
b_DDRA1. EQU %00000010 ;PTA1 Data Direction
b_DDRA0. EQU %00000001 ;PTA0 Data Direction
DDRB EQU $05 ;Port B Data Direction
b_DDRB7 EQU 7 ;PTB7 Data Direction
b_DDRB6 EQU 6 ;PTB6 Data Direction
b_DDRB5 EQU 5 ;PTB5 Data Direction
b_DDRB4 EQU 4 ;PTB4 Data Direction
b_DDRB3 EQU 3 ;PTB3 Data Direction
b_DDRB2 EQU 2 ;PTB2 Data Direction
b_DDRB1 EQU 1 ;PTB1 Data Direction
b_DDRB0 EQU 0 ;PTB0 Data Direction
b_DDRB7. EQU %10000000 ;PTB7 Data Direction
b_DDRB6. EQU %01000000 ;PTB6 Data Direction
b_DDRB5. EQU %00100000 ;PTB5 Data Direction
b_DDRB4. EQU %00010000 ;PTB4 Data Direction
b_DDRB3. EQU %00001000 ;PTB3 Data Direction
b_DDRB2. EQU %00000100 ;PTB2 Data Direction
b_DDRB1. EQU %00000010 ;PTB1 Data Direction
b_DDRB0. EQU %00000001 ;PTB0 Data Direction
DDRC EQU $06 ;Port C Data Direction
b_DDRC7 EQU 7 ;PTC7 Data Direction
b_DDRC6 EQU 6 ;PTC6 Data Direction
b_DDRC5 EQU 5 ;PTC5 Data Direction
b_DDRC4 EQU 4 ;PTC4 Data Direction
b_DDRC3 EQU 3 ;PTC3 Data Direction
b_DDRC2 EQU 2 ;PTC2 Data Direction
b_DDRC1 EQU 1 ;PTC1 Data Direction
b_DDRC0 EQU 0 ;PTC0 Data Direction
b_DDRC7. EQU %10000000 ;PTC7 Data Direction
b_DDRC6. EQU %01000000 ;PTC6 Data Direction
b_DDRC5. EQU %00100000 ;PTC5 Data Direction
b_DDRC4. EQU %00010000 ;PTC4 Data Direction
b_DDRC3. EQU %00001000 ;PTC3 Data Direction
b_DDRC2. EQU %00000100 ;PTC2 Data Direction
b_DDRC1. EQU %00000010 ;PTC1 Data Direction
b_DDRC0. EQU %00000001 ;PTC0 Data Direction
DDRD EQU $07 ;Port D Data Direction
b_DDRD7 EQU 7 ;PTD7 Data Direction
b_DDRD6 EQU 6 ;PTD6 Data Direction
b_DDRD5 EQU 5 ;PTD5 Data Direction
b_DDRD4 EQU 4 ;PTD4 Data Direction
b_DDRD3 EQU 3 ;PTD3 Data Direction
b_DDRD2 EQU 2 ;PTD2 Data Direction
b_DDRD1 EQU 1 ;PTD1 Data Direction
b_DDRD0 EQU 0 ;PTD0 Data Direction
b_DDRD7. EQU %10000000 ;PTD7 Data Direction
b_DDRD6. EQU %01000000 ;PTD6 Data Direction
b_DDRD5. EQU %00100000 ;PTD5 Data Direction
b_DDRD4. EQU %00010000 ;PTD4 Data Direction
b_DDRD3. EQU %00001000 ;PTD3 Data Direction
b_DDRD2. EQU %00000100 ;PTD2 Data Direction
b_DDRD1. EQU %00000010 ;PTD1 Data Direction
b_DDRD0. EQU %00000001 ;PTD0 Data Direction
PTE EQU $08 ;I/O PORT E
PTE4 EQU 4 ;PTE4 Input/Output Value
PTE3 EQU 3 ;PTE3 Input/Output Value
PTE2 EQU 2 ;PTE2 Input/Output Value
PTE1 EQU 1 ;PTE1 Input/Output Value
PTE0 EQU 0 ;PTE0 Input/Output Value
PTE4. EQU %00010000 ;PTE4 Input/Output Value
PTE3. EQU %00001000 ;PTE3 Input/Output Value
PTE2. EQU %00000100 ;PTE2 Input/Output Value
PTE1. EQU %00000010 ;PTE1 Input/Output Value
PTE0. EQU %00000001 ;PTE0 Input/Output Value
DDRE EQU $09 ;Port E Data Direction
b_DDRE4 EQU 4 ;PTE4 Data Direction
b_DDRE3 EQU 3 ;PTE3 Data Direction
b_DDRE2 EQU 2 ;PTE2 Data Direction
b_DDRE1 EQU 1 ;PTE1 Data Direction
b_DDRE0 EQU 0 ;PTE0 Data Direction
b_DDRE4. EQU %00010000 ;PTE4 Data Direction
b_DDRE3. EQU %00001000 ;PTE3 Data Direction
b_DDRE2. EQU %00000100 ;PTE2 Data Direction
b_DDRE1. EQU %00000010 ;PTE1 Data Direction
b_DDRE0. EQU %00000001 ;PTE0 Data Direction
*************************************************************
* TIM - Timer Interface Module
*************************************************************
* Timer
TSC EQU $0A ;Timer status and control
b_TOF equ 7 ; TIM overflow flag [r/o]
b_TOIE equ 6 ; =1 TOF interrupt enable
b_TSTOP equ 5 ; =1 TIM counter stopped
b_TRST equ 4 ; =1 clr TIM cntr & prescalar [w/o]
b_PS2 equ 2 ; 目
b_PS1 equ 1 ; ⌨️ 快捷键说明
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