📄 ad9954.asm
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;======================================================================
;
; Author : ADI - Apps
;
; Date : May 2003
;
; File : ad9954.asm
;
; Description : serial control mode.
; we assume that master clock is 27 MHz and multiplied by 10
; ADUC832 is used to control ad9854. The core clock is 2.097152MHz
;
;======================================================================
$MOD832 ; Use ADuC832 predefined Symbols
;define instruction byte for each register.
CFR1 EQU 00H
CFR2 EQU 01H
ASF EQU 02H
ARR EQU 03H
FTW0 EQU 04H
POW0 EQU 05H
FTW1 EQU 06H
NLSCW EQU 07H
PLSCW EQU 08H
RSCW0 EQU 07H
RSCW1 EQU 08H
RSCW2 EQU 09H
RSCW3 EQU 0AH
RAM EQU 0BH
;======================================================================
;DEFINE CONTROL PINS OF ADUC832 FOR THE PURPOSE OF AD9954 CONTROL.
;Customers should define the pins according to their design.
;If P0 is used as the control port, pull-up resistors should be added to each pin of P0.
;======================================================================
SCLOCK EQU P2.0
SDI EQU P3.3
SDO EQU P0.6
CSB EQU P3.4
RESET EQU P2.3
CLKM EQU P2.2
PWRD EQU P2.1
IORST EQU P3.5
FUD EQU P2.7
OSK EQU P2.6
PS1 EQU P2.5
PS0 EQU P2.4
;======================================================================
CSEG ; Defines the following as a segment of code
ORG 0000H ; Load Code at '0'
JMP MAIN ; Jump to MAIN
;======================================================================
ORG 0003h ; (INT0 ISR)
CLR C
RETI ; Return from Interrupt
;======================================================================
ORG 0070h
MAIN: ; (main program)
;======================================================================
;initialization
;after reset of aduc832, the default status of IO ports are 0xFFH
;we should set the status of these ports as we need
;======================================================================
CLR CLKM
CLR SCLOCK
CLR PWRD
CLR IORST
CLR FUD
CLR PS0
CLR PS1
CLR RB
CLR OSK
CLR SDO
CLR RESET
CLR CSB
;======================================================================
;SINGLE TONE MODE
;CFR1 keeps the default value
;Set CFR2 to multiply the REFCLK 10 times
;Then set the FTW0 as 20MHz
;======================================================================
MOV A,#CFR2
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#54H ; REFCLK is multiplied by 10, SET VCO Gain
CALL WRITEBYTE
MOV A,#FTW0 ; FTW0=20MHz
CALL WRITEBYTE
MOV A,#012H
CALL WRITEBYTE
MOV A,#0F6H
CALL WRITEBYTE
MOV A,#84H
CALL WRITEBYTE
MOV A,#0BEH
CALL WRITEBYTE
SETB CSB ; disable CSB
CLR FUD ; IO update
SETB FUD
NOP
CLR FUD
SETB IT0 ; INT0 edge triggered
SETB EA ; enable inturrupts
SETB EX0 ; enable INT0
SETB C
JC $ ; WAITING FOR Interrupt
;======================================================================
;Linear sweep mode.
;First, enable Linear sweep mode by setting CFR1, then write to FTW1 of 40MHz and FTW0 remaining 20MHz
;Then setting the NLSCW and PLSCW to configure the falling/rising sweep ramp rate word and delta frequency tuning word
;By toggling PS0 to get the different direction of sweeping.
;======================================================================
LINEAR: CLR CSB
MOV A,#CFR1
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#20H ;Enable Linear Sweep mode
CALL WRITEBYTE
MOV A,#02H ; Enable SDO
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#FTW1 ; FTW1=40MHz
CALL WRITEBYTE
MOV A,#25H
CALL WRITEBYTE
MOV A,#0EDH
CALL WRITEBYTE
MOV A,#09H
CALL WRITEBYTE
MOV A,#7BH
CALL WRITEBYTE
MOV A,#NLSCW
CALL WRITEBYTE
MOV A,#0FFH ;setting the rising Sweep Ramp Rate Word=FFH
CALL WRITEBYTE
MOV A,#00H ; Setting the rising Delta Frequency Tuning word=0.0001MHz
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#09FH
CALL WRITEBYTE
MOV A,#PLSCW
CALL WRITEBYTE
MOV A,#0FFH ;setting the rising Sweep Ramp Rate Word=FFH
CALL WRITEBYTE
MOV A,#00H ; Setting the rising Delta Frequency Tuning word=0.0001MHz
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#09FH
CALL WRITEBYTE
SETB FUD
CLR FUD
SETB CSB
SETB C
MOV A,#64H
LINEARS: CPL PS0 ; Toggle PS0 to switch Linear Sweep direction
CALL DELAY
JC LINEARS
;======================================================================
;RAM controlled mode.
;First, enable RAM controlled mode by setting CFR1
;Then, write to RSCW0~RSCW3 to set the begining/ending address and the ramp rate of the four RAM Segment.
;Then, write data to RAM
;Finally, implement the Direct Switch Mode,Ramp-up mode,Bi-directional Ramp Mode,Continuous Bi-directional Ramp Mode and
;Continuous Bi-directional Ramp mode.
;======================================================================
;Write to CFR1 to enable RAM controlled mode
CLR PS0
CLR PS1
CLR CSB
MOV A,#CFR1
CALL WRITEBYTE
MOV A,#80H ;enable RAM controlled mode
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#02H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
SETB FUD
CLR FUD
;write to RSCW0~RSCW3 to set the begining/ending address and the ramp rate of the four RAM Segment.
;Configure the four RAM segment as Direct switch Mode.
MOV A,#RSCW0
CALL WRITEBYTE
MOV A,#0FFH ;ramp rate as FFFFH
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#07H ;beginning address=000H ending adress=007H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#RSCW1
CALL WRITEBYTE
MOV A,#0FFH ;ramp rate as FFFFH
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#00H ;beginning address=100H ending adress=100H
CALL WRITEBYTE
MOV A,#01H
CALL WRITEBYTE
MOV A,#04H
CALL WRITEBYTE
MOV A,#RSCW2
CALL WRITEBYTE
MOV A,#0FFH ;ramp rate as FFFFH
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#00H ;beginning address=200H ending adress=200H
CALL WRITEBYTE
MOV A,#02H
CALL WRITEBYTE
MOV A,#08H
CALL WRITEBYTE
MOV A,#RSCW3
CALL WRITEBYTE
MOV A,#0FFH ;ramp rate as FFFFH
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#00H ;beginning address=300H ending adress=300H
CALL WRITEBYTE
MOV A,#03H
CALL WRITEBYTE
MOV A,#0CH
CALL WRITEBYTE
SETB CSB
SETB FUD
CLR FUD
;write data to RAM
RAMWRITE: CLR PS0
CLR PS1
MOV R7,#20H
MOV DPTR,#DATALIST0
CLR CSB
MOV A,#RAM
CALL WRITEBYTE
REWRITE0: CLR A
MOVC A,@A+DPTR
CALL WRITEBYTE
INC DPTR
DJNZ R7,REWRITE0
SETB PS0
MOV DPTR,#DATALIST1
MOV R7,#04
MOV A,#RAM
CALL WRITEBYTE
REWRITE1: CLR A
MOVC A,@A+DPTR
CALL WRITEBYTE
INC DPTR
DJNZ R7,REWRITE1
SETB PS1
CLR PS0
MOV DPTR,#DATALIST2
MOV R7,#04
MOV A,#RAM
CALL WRITEBYTE
REWRITE2: CLR A
MOVC A,@A+DPTR
CALL WRITEBYTE
INC DPTR
DJNZ R7,REWRITE2
SETB PS0
SETB PS1
MOV DPTR,#DATALIST3
MOV R7,#04
MOV A,#RAM
CALL WRITEBYTE
REWRITE3: CLR A
MOVC A,@A+DPTR
CALL WRITEBYTE
INC DPTR
DJNZ R7,REWRITE3
SETB CSB
SETB FUD
CLR FUD
;Direct switch mode by changing the value of PS0 and PS1
SWITCH: CLR PS0
CLR PS1
MOV A,#34H
CALL DELAY
SETB PS0
CALL DELAY
SETB PS1
CLR PS0
CALL DELAY
SETB PS0
CALL DELAY
SETB C
JC $
;RAMUP mode
RAMPUP: CLR PS0
CLR PS1
CLR CSB
MOV A,#RSCW0 ; configure RSCW0 as rampup mode.
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#07H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#20H
CALL WRITEBYTE
SETB CSB
SETB FUD
CLR FUD
SETB C
JC $
;bi-directional ramp mode
BI: CLR PS0
CLR PS1
CLR CSB
MOV A,#RSCW0 ; configure RSCW0 as bi-directional ramp mode.
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#07H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#40H
CALL WRITEBYTE
SETB CSB
SETB FUD
CLR FUD
SETB C
MOV A,#34H
BIDI: CALL DELAY ; Toggling PS0 to get the different ramp direction
CPL PS0
JC BIDI
;continuous bi-directional ramp mode
CON: CLR PS0
CLR PS1
CLR CSB
MOV A,#RSCW0 ; configure RSCW0 as continuous bi-directional ramp mode.
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#07H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#60H
CALL WRITEBYTE
SETB CSB
SETB FUD
CLR FUD
SETB C
JC $
;continuous recirculate mode
RECIR: CLR PS0
CLR PS1
CLR CSB
MOV A,#RSCW0 ; configure RSCW0 as continuous recirculate mode.
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#0FFH
CALL WRITEBYTE
MOV A,#07H
CALL WRITEBYTE
MOV A,#00H
CALL WRITEBYTE
MOV A,#80H
CALL WRITEBYTE
SETB CSB
SETB FUD
CLR FUD
SETB C
JC $
; Subroutines
;======================================================================
; write 8 bits to ad9954
; MSB first
; implemented by left-shifting the A register
;======================================================================
WRITEBYTE:
CLR C
MOV R0,#08H
LOOP: RLC A
MOV SDI,C ;prepare data on SDI
CLR SCLOCK ;give a pulse on sclk
SETB SCLOCK
CLR SCLOCK
DJNZ R0,LOOP
RET
DELAY: ; Delays by 100ms * A
; 100mSec based on 2.097152MHZ
; Core Clock
; i.e. default ADuC832 Clock
MOV R1,A ; Acc holds delay variable
DLY0: MOV R2,#022h ; Set up delay loop0
DLY1: MOV R3,#0FFh ; Set up delay loop1
DJNZ R3,$ ; Dec R3 & Jump here until R3 is 0
DJNZ R2,DLY1 ; Dec R2 & Jump DLY1 until R2 is 0
DJNZ R1,DLY0 ; Dec R1 & Jump DLY0 until R1 is 0
RET ; Return from subroutine
;The data list written to RAM
DATALIST0:
DB 055H,055H,055H,055H ;90MHz
DB 04BH,0DAH,012H,0F7H ;80MHz
DB 042H,05EH,0D0H,098H ;70MHz
DB 038H,0E3H,08EH,039H ;60MHz
DB 02FH,068H,04BH,0DAH ;50MHz
DB 025H,0EDH,009H,07BH ;40MHz
DB 01CH,071H,0C7H,01CH ;30MHz
DB 012H,0F6H,084H,0BEH ;20MHz
DATALIST1:
DB 01CH,071H,0C7H,01CH ;30MHz
DATALIST2:
DB 025H,0EDH,009H,07BH ;40MHz
DATALIST3:
DB 02FH,068H,04BH,0DAH ;50MHz
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