__projnav.log

用于FPGA向DSP传送数据的接口

Analysis of file <"fpgatodsp.prj"> failed.
--> 

Total memory usage is 77196 kilobytes

Number of errors   :   14 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "fpgatodsp.v"
Module <fpgatodsp> compiled
No errors in compilation
Analysis of file <"fpgatodsp.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <fpgatodsp>.
Module <fpgatodsp> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <fpgatodsp>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpgatodsp>.
    Related source file is "fpgatodsp.v".
WARNING:Xst:1778 - Inout <dout<31:16>> is assigned but never used.
WARNING:Xst:1778 - Inout <dout<3:0>> is assigned but never used.
WARNING:Xst:653 - Signal <xc2out> is used but never assigned. Tied to value 01000101011001111000100110101011.
WARNING:Xst:653 - Signal <xc1out> is used but never assigned. Tied to value 00010010001101000101011001111000.
WARNING:Xst:653 - Signal <xc1out1> is used but never assigned. Tied to value 00100011010001010110011110001001.
WARNING:Xst:653 - Signal <xc1out2> is used but never assigned. Tied to value 00110100010101100111100010011010.
WARNING:Xst:653 - Signal <xc2out1> is used but never assigned. Tied to value 01010110011110001001101010111100.
WARNING:Xst:653 - Signal <xc2out2> is used but never assigned. Tied to value 01100111100010011010101111001101.
    Found 1-bit register for signal <interrupt>.
    Found 12-bit register for signal <daout>.
    Found 32-bit tristate buffer for signal <dout>.
    Found 11-bit up counter for signal <cnt>.
    Found 32-bit register for signal <dout_reg>.
    Summary:
	inferred   1 Counter(s).
	inferred  45 D-type flip-flop(s).
	inferred  32 Tristate(s).
Unit <fpgatodsp> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 11-bit up counter                 : 1
# Registers                        : 3
 1-bit register                    : 1
 12-bit register                   : 1
 32-bit register                   : 1
# Tristates                        : 1
 32-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <dout_reg_31> (without init value) has a constant value of 0 in block <fpgatodsp>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <dout_reg_27> (without init value) has a constant value of 0 in block <fpgatodsp>.
Register <dout_reg_28> equivalent to <dout_reg_20> has been removed
Register <dout_reg_24> equivalent to <dout_reg_16> has been removed
Register <dout_reg_30> equivalent to <dout_reg_15> has been removed
Register <dout_reg_8> equivalent to <dout_reg_0> has been removed
Register <dout_reg_16> equivalent to <dout_reg_0> has been removed
Register <dout_reg_17> equivalent to <dout_reg_1> has been removed
Register <dout_reg_19> equivalent to <dout_reg_2> has been removed
Register <dout_reg_12> equivalent to <dout_reg_4> has been removed
Register <dout_reg_20> equivalent to <dout_reg_4> has been removed
Register <dout_reg_21> equivalent to <dout_reg_5> has been removed
Register <dout_reg_29> equivalent to <dout_reg_13> has been removed
Register <dout_reg_26> equivalent to <dout_reg_11> has been removed
Register <dout_reg_25> equivalent to <dout_reg_9> has been removed

Optimizing unit <fpgatodsp> ...
Loading device for application Rf_Device from file '4vsx35.nph' in environment D:/xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fpgatodsp, actual ratio is 0.
FlipFlop dout_reg_11 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_4 has been replicated 3 time(s) to handle iob=true attribute.
FlipFlop dout_reg_13 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_0 has been replicated 3 time(s) to handle iob=true attribute.
FlipFlop dout_reg_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_9 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_reg_15 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vsx35ff668-12 

 Number of Slices:                      38  out of  15360     0%  
 Number of Slice Flip Flops:            54  out of  30720     0%  
 Number of 4 input LUTs:                43  out of  30720     0%  
 Number of bonded IOBs:                 71  out of    450    15%  
 Number of GCLKs:                        3  out of     32     9%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
nwr                                | BUFGP                  | 12    |
nrd                                | BUFGP                  | 30    |
CLK                                | BUFGP                  | 12    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -12

   Minimum period: 2.753ns (Maximum Frequency: 363.280MHz)
   Minimum input arrival time before clock: 2.932ns
   Maximum output required time after clock: 3.935ns
   Maximum combinational path delay: 5.269ns

=========================================================================


Project Navigator Auto-Make Log File
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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\favorites\fpgadsp/_ngo -nt timestamp
-uc fd_constraints.ucf -p xc4vsx35-ff668-12 fpgatodsp.ngc fpgatodsp.ngd 

Reading NGO file 'D:/Favorites/fpgadsp/fpgatodsp.ngc' ...

Applying constraints in "fd_constraints.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "fpgatodsp.ngd" ...

Writing NGDBUILD log file "fpgatodsp.bld"...

NGDBUILD done.




Started process "Map".

Using target part "4vsx35ff668-12".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   19
Logic Utilization:
  Number of Slice Flip Flops:          12 out of  30,720    1%
  Number of 4 input LUTs:              34 out of  30,720    1%
Logic Distribution:
  Number of occupied Slices:                           26 out of  15,360    1%
    Number of Slices containing only related logic:      26 out of      26  100%
    Number of Slices containing unrelated logic:          0 out of      26    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             40 out of  30,720    1%
  Number used as logic:                 34
  Number used as a route-thru:           6
  Number of bonded IOBs:               71 out of     448   15%
  Number of BUFG/BUFGCTRLs:             3 out of      32    9%
    Number used as BUFGs:                3
    Number used as BUFGCTRLs:            0

Total equivalent gate count for design:  792
Additional JTAG gate count for IOBs:  3,408
Peak Memory Usage:  202 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "fpgatodsp_map.mrp" for details.




Started process "Place & Route".




Constraints file: fpgatodsp.pcf.
Loading device for application Rf_Device from file '4vsx35.nph' in environment
D:/xilinx.
   "fpgatodsp" is an NCD, version 3.1, device xc4vsx35, package ff668, speed -12
This design is using the default stepping level (major silicon revision) for
this device (1). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.200 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PREVIEW 1.57 2005-08-24".


Device Utilization Summary:

   Number of BUFGs                     3 out of 32      9%
   Number of External IOBs            71 out of 448    15%
      Number of LOCed IOBs            71 out of 71    100%

   Number of OLOGICs                  42 out of 448     9%
   Number of Slices                   26 out of 15360   1%
      Number of SLICEMs                0 out of 7680    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

WARNING:Par:276 - The signal addr<2>_IBUF has no load
WARNING:Par:276 - The signal addr<3>_IBUF has no load
WARNING:Par:276 - The signal addr<5>_IBUF has no load
WARNING:Par:276 - The signal addr<6>_IBUF has no load
WARNING:Par:276 - The signal addr<7>_IBUF has no load
WARNING:Par:276 - The signal addr<9>_IBUF has no load
WARNING:Par:276 - The signal addr<10>_IBUF has no load
WARNING:Par:276 - The signal addr<11>_IBUF has no load
WARNING:Par:276 - The signal addr<12>_IBUF has no load
WARNING:Par:276 - The signal addr<13>_IBUF has no load
WARNING:Par:276 - The signal addr<14>_IBUF has no load
WARNING:Par:276 - The signal addr<15>_IBUF has no load
WARNING:Par:276 - The signal addr<16>_IBUF has no load
WARNING:Par:276 - The signal addr<17>_IBUF has no load
WARNING:Par:276 - The signal addr<18>_IBUF has no load
WARNING:Par:276 - The signal addr<19>_IBUF has no load
WARNING:Par:276 - The signal addr<1>_IBUF has no load

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9898e9) REAL time: 5 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs 

Phase 3.2
......
WARNING:Place:644 - A clock IOB  clock component is not placed at an optimal
   clock IOB site  The clock IOB component <nrd> is placed at site IOB_X0Y131.
   The clock IO site can use the fast path between the IO and the Clock
   buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
   normally an ERROR but the environment variable
   XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING is set allowing your design to continue.
WARNING:Place:644 - A clock IOB  clock component is not placed at an optimal
   clock IOB site  The clock IOB