📄 __projnav.log
字号:
Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "fpgatodsp.v"Module <fpgatodsp> compiledERROR:HDLCompilers:247 - "fpgatodsp.v" line 64 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 64 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 65 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 65 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 66 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 66 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 67 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 67 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 68 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 68 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 69 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 69 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 70 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 70 Illegal left hand side of blocking assignmentAnalysis of file <"fpgatodsp.prj"> failed.--> Total memory usage is 77196 kilobytesNumber of errors : 14 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "fpgatodsp.v"Module <fpgatodsp> compiledERROR:HDLCompilers:247 - "fpgatodsp.v" line 64 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 64 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 65 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 65 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 66 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 66 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 67 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 67 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 68 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 68 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 69 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 69 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 70 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 70 Illegal left hand side of nonblocking assignmentAnalysis of file <"fpgatodsp.prj"> failed.--> Total memory usage is 77196 kilobytesNumber of errors : 14 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "fpgatodsp.v"ERROR:HDLCompilers:26 - "fpgatodsp.v" line 30 unexpected token: 'reg'ERROR:HDLCompilers:28 - "fpgatodsp.v" line 64 'dout' has not been declaredERROR:HDLCompilers:28 - "fpgatodsp.v" line 65 'dout' has not been declaredERROR:HDLCompilers:28 - "fpgatodsp.v" line 66 'dout' has not been declaredERROR:HDLCompilers:28 - "fpgatodsp.v" line 67 'dout' has not been declaredERROR:HDLCompilers:28 - "fpgatodsp.v" line 68 'dout' has not been declaredERROR:HDLCompilers:28 - "fpgatodsp.v" line 69 'dout' has not been declaredERROR:HDLCompilers:28 - "fpgatodsp.v" line 70 'dout' has not been declaredERROR:HDLCompilers:28 - "fpgatodsp.v" line 77 'dout' has not been declaredERROR:HDLCompilers:208 - "fpgatodsp.v" line 21 Port reference 'dout' was not declared as input, inout or outputModule <fpgatodsp> compiledAnalysis of file <"fpgatodsp.prj"> failed.--> Total memory usage is 77196 kilobytesNumber of errors : 10 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "fpgatodsp.v"ERROR:HDLCompilers:121 - "fpgatodsp.v" line 31 Illegal redeclaration of inout 'dout' as a regModule <fpgatodsp> compiledAnalysis of file <"fpgatodsp.prj"> failed.--> Total memory usage is 77196 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "fpgatodsp.v"Module <fpgatodsp> compiledERROR:HDLCompilers:247 - "fpgatodsp.v" line 65 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 65 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 66 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 66 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 67 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 67 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 68 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 68 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 69 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 69 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 70 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 70 Illegal left hand side of nonblocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 71 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:106 - "fpgatodsp.v" line 71 Illegal left hand side of nonblocking assignmentAnalysis of file <"fpgatodsp.prj"> failed.--> Total memory usage is 77196 kilobytesNumber of errors : 14 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "fpgatodsp.v"Module <fpgatodsp> compiledERROR:HDLCompilers:247 - "fpgatodsp.v" line 65 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 65 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 66 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 66 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 67 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 67 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 68 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 68 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 69 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 69 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 70 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 70 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 71 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 71 Illegal left hand side of blocking assignmentAnalysis of file <"fpgatodsp.prj"> failed.--> Total memory usage is 77196 kilobytesNumber of errors : 14 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "fpgatodsp.v"ERROR:HDLCompilers:121 - "fpgatodsp.v" line 31 Illegal redeclaration of inout 'dout' as a regModule <fpgatodsp> compiledAnalysis of file <"fpgatodsp.prj"> failed.--> Total memory usage is 77196 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "fpgatodsp.v"Module <fpgatodsp> compiledERROR:HDLCompilers:247 - "fpgatodsp.v" line 65 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 65 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 66 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 66 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 67 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 67 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 68 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 68 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 69 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 69 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 70 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 70 Illegal left hand side of blocking assignmentERROR:HDLCompilers:247 - "fpgatodsp.v" line 71 Reference to vector wire 'dout' is not a legal reg or variable lvalueERROR:HDLCompilers:44 - "fpgatodsp.v" line 71 Illegal left hand side of blocking assignment⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -