__projnav.log

用于FPGA向DSP传送数据的接口

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs 

Phase 3.2
......
WARNING:Place:644 - A clock IOB  clock component is not placed at an optimal
   clock IOB site  The clock IOB component <nrd> is placed at site IOB_X0Y131.
   The clock IO site can use the fast path between the IO and the Clock
   buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
   normally an ERROR but the environment variable
   XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING is set allowing your design to continue.
WARNING:Place:644 - A clock IOB  clock component is not placed at an optimal
   clock IOB site  The clock IOB component <CLK> is placed at site IOB_X1Y58.
   The clock IO site can use the fast path between the IO and the Clock
   buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
   normally an ERROR but the environment variable
   XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING is set allowing your design to continue.


Phase 3.2 (Checksum:98a237) REAL time: 6 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 6 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 6 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 6 secs 

Phase 7.8
.
Phase 7.8 (Checksum:9b885d) REAL time: 6 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 6 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 6 secs 

Phase 10.27
Phase 10.27 (Checksum:5f5e0f6) REAL time: 6 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 6 secs 

Writing design to file fpgatodsp.ncd


Total REAL time to Placer completion: 6 secs 
Total CPU time to Placer completion: 5 secs 

Starting Router

Phase 1: 237 unrouted;       REAL time: 7 secs 

Phase 2: 168 unrouted;       REAL time: 8 secs 

Phase 3: 20 unrouted;       REAL time: 8 secs 

Phase 4: 0 unrouted;       REAL time: 8 secs 

Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 6 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           nrd_BUFGP |BUFGCTRL_X0Y16| No   |   30 |  0.321     |  2.361      |
+---------------------+--------------+------+------+------------+-------------+
|           CLK_BUFGP | BUFGCTRL_X0Y1| No   |    5 |  0.014     |  1.974      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 11 secs 
Total CPU time to PAR completion: 9 secs 

Peak Memory Usage:  176 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 19
Number of info messages: 1

Writing design to file fpgatodsp.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '4vsx35.nph' in environment
D:/xilinx.
   "fpgatodsp" is an NCD, version 3.1, device xc4vsx35, package ff668, speed -12
This design is using the default stepping level (major silicon revision) for
this device (1). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.

Analysis completed Tue Aug 14 22:34:35 2007
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 6 secs 


Project Navigator Auto-Make Log File
-------------------------------------







Started process "Generate Programming File".

WARNING:PhysDesignRules:367 - The signal <addr<2>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<3>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<5>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<6>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<7>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<9>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<10>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<11>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<12>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<13>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<14>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<15>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<16>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<17>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<18>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<19>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <addr<1>_IBUF> is incomplete. The
   signal does not drive any load pins in the design.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "fpgatodsp.v"
Module <fpgatodsp> compiled
No errors in compilation
Analysis of file <"fpgatodsp.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <fpgatodsp>.
Module <fpgatodsp> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <fpgatodsp>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fpgatodsp>.
    Related source file is "fpgatodsp.v".
WARNING:Xst:653 - Signal <xc2out> is used but never assigned. Tied to value 01000101011001111000100110101011.
WARNING:Xst:653 - Signal <xc1out> is used but never assigned. Tied to value 00010010001101000101011001111000.
WARNING:Xst:653 - Signal <xc1out1> is used but never assigned. Tied to value 00100011010001010110011110001001.
WARNING:Xst:653 - Signal <xc1out2> is used but never assigned. Tied to value 00110100010101100111100010011010.
WARNING:Xst:653 - Signal <xc2out1> is used but never assigned. Tied to value 01010110011110001001101010111100.
WARNING:Xst:653 - Signal <xc2out2> is used but never assigned. Tied to value 01100111100010011010101111001101.
    Found 1-bit register for signal <interrupt>.
    Found 32-bit register for signal <dout>.
    Found 32-bit 6-to-1 multiplexer for signal <$n0003> created at line 56.
    Found 11-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred  33 D-type flip-flop(s).
	inferred  32 Multiplexer(s).
Unit <fpgatodsp> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 11-bit up counter                 : 1
# Registers                        : 2
 1-bit register                    : 1
 32-bit register                   : 1
# Multiplexers                     : 1
 32-bit 6-to-1 multiplexer         : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch dout_3 hinder the constant cleaning in the block fpgatodsp.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1710 - FF/Latch  <dout_31> (without init value) has a constant value of 0 in block <fpgatodsp>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <dout_27> (without init value) has a constant value of 0 in block <fpgatodsp>.
Register <dout_8> equivalent to <dout_0> has been removed
Register <dout_24> equivalent to <dout_0> has been removed
Register <dout_16> equivalent to <dout_0> has been removed
Register <dout_17> equivalent to <dout_1> has been removed
Register <dout_19> equivalent to <dout_2> has been removed
Register <dout_12> equivalent to <dout_4> has been removed
Register <dout_20> equivalent to <dout_4> has been removed
Register <dout_28> equivalent to <dout_4> has been removed
Register <dout_21> equivalent to <dout_5> has been removed
Register <dout_25> equivalent to <dout_9> has been removed
Register <dout_26> equivalent to <dout_11> has been removed
Register <dout_29> equivalent to <dout_13> has been removed
Register <dout_30> equivalent to <dout_15> has been removed

Optimizing unit <fpgatodsp> ...
Loading device for application Rf_Device from file '4vsx35.nph' in environment D:/xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block fpgatodsp, actual ratio is 0.
FlipFlop dout_15 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_13 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_4 has been replicated 3 time(s) to handle iob=true attribute.
FlipFlop dout_11 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_9 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_0 has been replicated 3 time(s) to handle iob=true attribute.
FlipFlop dout_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop dout_1 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vsx35ff668-12 

 Number of Slices:                      32  out of  15360     0%  
 Number of Slice Flip Flops:            42  out of  30720     0%  
 Number of 4 input LUTs:                37  out of  30720     0%  
 Number of bonded IOBs:                 57  out of    450    12%  
 Number of GCLKs:                        2  out of     32     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 12    |
nrd                                | BUFGP                  | 30    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -12

   Minimum period: 2.837ns (Maximum Frequency: 352.522MHz)
   Minimum input arrival time before clock: 2.893ns
   Maximum output required time after clock: 3.935ns
   Maximum combinational path delay: No path found

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\favorites\fpgatodsp/_ngo -nt
timestamp -uc fd_constraints.ucf -p xc4vsx35-ff668-12 fpgatodsp.ngc
fpgatodsp.ngd 

Reading NGO file 'D:/Favorites/fpgatodsp/fpgatodsp.ngc' ...