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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling verilog file "fpgatodsp.v"Module <fpgatodsp> compiledNo errors in compilationAnalysis of file <"fpgatodsp.prj"> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <fpgatodsp>.Module <fpgatodsp> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <fpgatodsp>. Related source file is "fpgatodsp.v".WARNING:Xst:653 - Signal <xc2out> is used but never assigned. Tied to value 01000101011001111000100110101011.WARNING:Xst:653 - Signal <xc1out> is used but never assigned. Tied to value 00010010001101000101011001111000.WARNING:Xst:653 - Signal <xc1out1> is used but never assigned. Tied to value 00100011010001010110011110001001.WARNING:Xst:653 - Signal <xc1out2> is used but never assigned. Tied to value 00110100010101100111100010011010.WARNING:Xst:653 - Signal <xc2out1> is used but never assigned. Tied to value 01010110011110001001101010111100.WARNING:Xst:653 - Signal <xc2out2> is used but never assigned. Tied to value 01100111100010011010101111001101. Found 1-bit register for signal <interrupt>. Found 32-bit register for signal <dout>. Found 32-bit 6-to-1 multiplexer for signal <$n0003> created at line 56. Found 5-bit up counter for signal <cnt>. Summary: inferred 1 Counter(s). inferred 33 D-type flip-flop(s). inferred 32 Multiplexer(s).Unit <fpgatodsp> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...MAC inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...DSP optimizations ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 1 5-bit up counter : 1# Registers : 2 1-bit register : 1 32-bit register : 1# Multiplexers : 1 32-bit 6-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1426 - The value init of the FF/Latch dout_3 hinder the constant cleaning in the block fpgatodsp. You should achieve better results by setting this init to 1.WARNING:Xst:1710 - FF/Latch <dout_31> (without init value) has a constant value of 0 in block <fpgatodsp>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dout_27> (without init value) has a constant value of 0 in block <fpgatodsp>.Register <dout_8> equivalent to <dout_0> has been removedRegister <dout_24> equivalent to <dout_0> has been removedRegister <dout_16> equivalent to <dout_0> has been removedRegister <dout_17> equivalent to <dout_1> has been removedRegister <dout_19> equivalent to <dout_2> has been removedRegister <dout_12> equivalent to <dout_4> has been removedRegister <dout_20> equivalent to <dout_4> has been removedRegister <dout_28> equivalent to <dout_4> has been removedRegister <dout_21> equivalent to <dout_5> has been removedRegister <dout_25> equivalent to <dout_9> has been removedRegister <dout_26> equivalent to <dout_11> has been removedRegister <dout_29> equivalent to <dout_13> has been removedRegister <dout_30> equivalent to <dout_15> has been removedOptimizing unit <fpgatodsp> ...Loading device for application Rf_Device from file '4vsx35.nph' in environment D:/xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block fpgatodsp, actual ratio is 0.FlipFlop dout_15 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop dout_13 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop dout_4 has been replicated 3 time(s) to handle iob=true attribute.FlipFlop dout_11 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop dout_9 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop dout_0 has been replicated 3 time(s) to handle iob=true attribute.FlipFlop dout_5 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop dout_2 has been replicated 1 time(s) to handle iob=true attribute.FlipFlop dout_1 has been replicated 1 time(s) to handle iob=true attribute.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 4vsx35ff668-12 Number of Slices: 22 out of 15360 0% Number of Slice Flip Flops: 36 out of 30720 0% Number of 4 input LUTs: 23 out of 30720 0% Number of bonded IOBs: 57 out of 450 12% Number of GCLKs: 2 out of 32 6% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+CLK | BUFGP | 6 |nrd | BUFGP | 30 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -12 Minimum period: 2.103ns (Maximum Frequency: 475.545MHz) Minimum input arrival time before clock: 2.893ns Maximum output required time after clock: 3.935ns Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\favorites\fpgatodsp/_ngo -nttimestamp -uc fd_constraints.ucf -p xc4vsx35-ff668-12 fpgatodsp.ngcfpgatodsp.ngd Reading NGO file 'D:/Favorites/fpgatodsp/fpgatodsp.ngc' ...Applying constraints in "fd_constraints.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "fpgatodsp.ngd" ...Writing NGDBUILD log file "fpgatodsp.bld"...NGDBUILD done.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\favorites\fpgatodsp/_ngo -nttimestamp -uc fd_constraints.ucf -p xc4vsx35-ff668-12 fpgatodsp.ngcfpgatodsp.ngd Reading NGO file 'D:/Favorites/fpgatodsp/fpgatodsp.ngc' ...Applying constraints in "fd_constraints.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "fpgatodsp.ngd" ...Writing NGDBUILD log file "fpgatodsp.bld"...NGDBUILD done.
Started process "Map".Using target part "4vsx35ff668-12".Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 22Logic Utilization: Number of Slice Flip Flops: 6 out of 30,720 1% Number of 4 input LUTs: 23 out of 30,720 1%Logic Distribution: Number of occupied Slices: 12 out of 15,360 1% Number of Slices containing only related logic: 12 out of 12 100% Number of Slices containing unrelated logic: 0 out of 12 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 23 out of 30,720 1% Number of bonded IOBs: 57 out of 448 12% Number of BUFG/BUFGCTRLs: 2 out of 32 6% Number used as BUFGs: 2 Number used as BUFGCTRLs: 0Total equivalent gate count for design: 426Additional JTAG gate count for IOBs: 2,736Peak Memory Usage: 202 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "fpgatodsp_map.mrp" for details.
Started process "Place & Route".Constraints file: fpgatodsp.pcf.Loading device for application Rf_Device from file '4vsx35.nph' in environmentD:/xilinx. "fpgatodsp" is an NCD, version 3.1, device xc4vsx35, package ff668, speed -12This design is using the default stepping level (major silicon revision) forthis device (1). Unless your design is targeted at devices of this steppinglevel, it is recommended that you explicitly specify the stepping level of theparts you will be using. This will allow the tools to take advantage of anyavailable performance and functional enhancements for this device. The lateststepping level for this device is '2'. Additional information on "steppinglevel" is available at support.xilinx.com.Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000Celsius)Initializing voltage to 1.200 Volts. (default - Range: 1.140 to 1.260 Volts)Device speed data version: "PREVIEW 1.57 2005-08-24".Device Utilization Summary: Number of BUFGs 2 out of 32 6% Number of ILOGICs 1 out of 448 1% Number of External IOBs 57 out of 448 12% Number of LOCed IOBs 57 out of 57 100% Number of OLOGICs 29 out of 448 6% Number of Slices 12 out of 15360 1% Number of SLICEMs 0 out of 7680 0%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)WARNING:Par:276 - The signal addr<2>_IBUF has no loadWARNING:Par:276 - The signal addr<3>_IBUF has no loadWARNING:Par:276 - The signal addr<5>_IBUF has no loadWARNING:Par:276 - The signal addr<6>_IBUF has no loadWARNING:Par:276 - The signal addr<7>_IBUF has no loadWARNING:Par:276 - The signal addr<9>_IBUF has no loadWARNING:Par:276 - The signal addr<10>_IBUF has no loadWARNING:Par:276 - The signal addr<11>_IBUF has no loadWARNING:Par:276 - The signal addr<12>_IBUF has no loadWARNING:Par:276 - The signal addr<13>_IBUF has no loadWARNING:Par:276 - The signal addr<14>_IBUF has no loadWARNING:Par:276 - The signal addr<15>_IBUF has no loadWARNING:Par:276 - The signal addr<16>_IBUF has no loadWARNING:Par:276 - The signal addr<17>_IBUF has no loadWARNING:Par:276 - The signal addr<18>_IBUF has no loadWARNING:Par:276 - The signal addr<19>_IBUF has no loadWARNING:Par:276 - The signal addr<1>_IBUF has no loadStarting PlacerPhase 1.1Phase 1.1 (Checksum:989859) REAL time: 5 secs ⌨️ 快捷键说明
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