📄 pn.rpt
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cpldfit: version H.38 Xilinx Inc.
Fitter Report
Design Name: pn Date: 4-11-2007, 10:41AM
Device Used: XA2C32A-6-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
22 /32 ( 69%) 23 /112 ( 21%) 8 /80 ( 10%) 22 /32 ( 69%) 16 /33 ( 48%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO CTC CTR CTS CTE
Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/16* 2/40 17/56 15/16 0/1 0/1 0/1 0/1
FB2 6/16 6/40 6/56 0/16 0/1 0/1 0/1 0/1
----- ------- ------- ----- --- --- --- ---
Total 22/32 8/80 23/112 15/32 0/2 0/2 0/2 0/2
CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable
* - Resource is exhausted
** Global Control Resources **
GCK GSR GTS
Used/Tot Used/Tot Used/Tot
1/3 0/1 0/4
Signal 'clk' mapped onto global clock net GCK0.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
| I : 0 1
Input : 0 0 | I/O : 10 24
Output : 15 15 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 4 4
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 16 16
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 15 Outputs **
Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init
Name Pts Inps No. Type Use STD Style Rate Use State
seq<10> 1 1 FB1_1 38 I/O O LVCMOS18 FAST DFF RESET
seq<11> 1 1 FB1_2 37 I/O O LVCMOS18 FAST DFF RESET
seq<12> 1 1 FB1_3 36 I/O O LVCMOS18 FAST DFF RESET
seq<13> 1 1 FB1_4 34 GTS/I/O O LVCMOS18 FAST DFF RESET
seq<14> 1 1 FB1_5 33 GTS/I/O O LVCMOS18 FAST DFF RESET
seq<15> 1 1 FB1_6 32 GTS/I/O O LVCMOS18 FAST DFF RESET
seq<1> 1 1 FB1_7 31 GTS/I/O O LVCMOS18 FAST DFF RESET
seq<2> 1 1 FB1_8 30 GSR/I/O O LVCMOS18 FAST DFF RESET
seq<3> 1 1 FB1_9 29 I/O O LVCMOS18 FAST DFF RESET
seq<4> 1 1 FB1_10 28 I/O O LVCMOS18 FAST DFF RESET
seq<5> 1 1 FB1_11 27 I/O O LVCMOS18 FAST DFF RESET
seq<6> 1 1 FB1_12 23 I/O O LVCMOS18 FAST DFF RESET
seq<7> 1 1 FB1_13 22 I/O O LVCMOS18 FAST DFF RESET
seq<8> 1 1 FB1_14 21 I/O O LVCMOS18 FAST DFF RESET
seq<9> 1 1 FB1_15 20 I/O O LVCMOS18 FAST DFF RESET
** 7 Buried Nodes **
Signal Total Total Loc Reg Reg Init
Name Pts Inps Use State
new_reg<4> 2 2 FB1_16 DFF RESET
registers_0 1 1 FB2_11 DFF RESET
registers<3> 1 1 FB2_12 DFF/S SET
registers<2> 1 1 FB2_13 DFF RESET
registers<1> 1 1 FB2_14 DFF/S SET
new_reg<2> 1 1 FB2_15 DFF RESET
new_reg<1> 1 1 FB2_16 DFF RESET
** 1 Inputs **
Signal Loc Pin Pin Pin I/O I/O
Name No. Type Use STD Style
clk FB2_5 43 GCK/I/O GCK LVCMOS18
Legend:
Pin No. - ~ - User Assigned
I/O Style - OD - OpenDrain
- PU - Pullup
- KPR - Keeper
- S - SchmittTrigger
- DG - DataGate
Reg Use - LATCH - Transparent latch
- DFF - D-flip-flop
- DEFF - D-flip-flop with clock enable
- TFF - T-flip-flop
- TDFF - Dual-edge-triggered T-flip-flop
- DDFF - Dual-edge-triggered flip-flop
- DDEFF - Dual-edge-triggered flip-flop with clock enable
/S (after any above flop/latch type) indicates initial state is Set
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
VRF - Vref
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
This function block is part of I/O Bank number: 2
Number of function block inputs used/remaining: 2/38
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 17/39
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
seq<10> 1 FB1_1 38 I/O O
seq<11> 1 FB1_2 37 I/O O
seq<12> 1 FB1_3 36 I/O O
seq<13> 1 FB1_4 34 GTS/I/O O
seq<14> 1 FB1_5 33 GTS/I/O O
seq<15> 1 FB1_6 32 GTS/I/O O
seq<1> 1 FB1_7 31 GTS/I/O O
seq<2> 1 FB1_8 30 GSR/I/O O
seq<3> 1 FB1_9 29 I/O O
seq<4> 1 FB1_10 28 I/O O
seq<5> 1 FB1_11 27 I/O O
seq<6> 1 FB1_12 23 I/O O
seq<7> 1 FB1_13 22 I/O O
seq<8> 1 FB1_14 21 I/O O
seq<9> 1 FB1_15 20 I/O O
new_reg<4> 2 FB1_16 19 I/O (b)
Signals Used by Logic in Function Block
1: registers<3> 2: registers_0
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
seq<10> X....................................... 1
seq<11> X....................................... 1
seq<12> X....................................... 1
seq<13> X....................................... 1
seq<14> X....................................... 1
seq<15> X....................................... 1
seq<1> X....................................... 1
seq<2> X....................................... 1
seq<3> X....................................... 1
seq<4> X....................................... 1
seq<5> X....................................... 1
seq<6> X....................................... 1
seq<7> X....................................... 1
seq<8> X....................................... 1
seq<9> X....................................... 1
new_reg<4> XX...................................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
This function block is part of I/O Bank number: 1
Number of function block inputs used/remaining: 6/34
Number of function block control terms used/remaining: 0/4
Number of PLA product terms used/remaining: 6/50
Signal Total Loc Pin Pin Pin CTC CTR CTS CTE
Name Pt No. Type Use
(unused) 0 FB2_1 39 I/O
(unused) 0 FB2_2 40 I/O
(unused) 0 FB2_3 41 I/O
(unused) 0 FB2_4 42 I/O
(unused) 0 FB2_5 43 GCK/I/O GCK
(unused) 0 FB2_6 44 GCK/I/O
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