pn.par

用VHDL语言编写的PN码产生程序

Release 7.1.04i par H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

WQ-98007498B40C::  Thu Apr 26 14:34:02 2007

par -w -intstyle ise -ol std -t 1 pn_map.ncd pn.ncd pn.pcf 


Constraints file: pn.pcf.
Loading device for application Rf_Device from file '4vfx12.nph' in environment
D:/Program Files/Xilinx ISE 7.1i.
   "pn" is an NCD, version 3.1, device xc4vfx12, package sf363, speed -12

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.200 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PREVIEW 1.57 2005-08-24".


Device Utilization Summary:

   Number of BUFGs                     1 out of 32      3%
   Number of External IOBs             3 out of 240     1%
      Number of LOCed IOBs             0 out of 3       0%

   Number of Slices                    5 out of 5472    1%
      Number of SLICEMs                0 out of 2736    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896b3) REAL time: 4 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 4 secs 

Phase 3.2



Phase 3.2 (Checksum:1c9c37d) REAL time: 5 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 5 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 5 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 5 secs 

Phase 7.8
.
Phase 7.8 (Checksum:990a29) REAL time: 5 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 5 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 5 secs 

Phase 10.27
Phase 10.27 (Checksum:5f5e0f6) REAL time: 5 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 5 secs 

Writing design to file pn.ncd


Total REAL time to Placer completion: 5 secs 
Total CPU time to Placer completion: 5 secs 

Starting Router

Phase 1: 44 unrouted;       REAL time: 6 secs 

Phase 2: 19 unrouted;       REAL time: 6 secs 

Phase 3: 0 unrouted;       REAL time: 6 secs 

Phase 4: 0 unrouted;       REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 5 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP | BUFGCTRL_X0Y0| No   |    5 |  0.002     |  1.882      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  144 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file pn.ncd



PAR done!