pn.mfd

用VHDL语言编写的PN码产生程序

MDF Database:  version 1.0
MDF_INFO | pn | XA2C32A-6-VQ44
MACROCELL | 0 | 0 | seq<10>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<10> := registers<3>;	// (1 pt, 1 inp)
   seq<10>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 1 | 11 | registers<3>_MC
ATTRIBUTES | 2155905796 | 0
OUTPUTMC | 16 | 0 | 14 | 0 | 15 | 0 | 0 | 0 | 1 | 0 | 2 | 0 | 3 | 0 | 4 | 0 | 5 | 0 | 6 | 0 | 7 | 0 | 8 | 0 | 9 | 0 | 10 | 0 | 11 | 0 | 12 | 0 | 13
INPUTS | 1 | new_reg<4>
INPUTMC | 1 | 0 | 15
EQ | 2 | 
   registers<3> := new_reg<4>;	// (1 pt, 1 inp)
   registers<3>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 15 | new_reg<4>_MC
ATTRIBUTES | 2155905792 | 0
OUTPUTMC | 1 | 1 | 11
INPUTS | 2 | registers<3>  | registers_0
INPUTMC | 2 | 1 | 11 | 1 | 10
EQ | 3 | 
   new_reg<4> := registers<3> & !registers_0
	# !registers<3> & registers_0;	// (2 pt, 2 inp)
   new_reg<4>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 1 | 10 | registers_0_MC
ATTRIBUTES | 2155905792 | 0
OUTPUTMC | 1 | 0 | 15
INPUTS | 1 | new_reg<1>
INPUTMC | 1 | 1 | 15
EQ | 2 | 
   registers_0 := new_reg<1>;	// (1 pt, 1 inp)
   registers_0.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 1 | 15 | new_reg<1>_MC
ATTRIBUTES | 2155905792 | 0
OUTPUTMC | 1 | 1 | 10
INPUTS | 1 | registers<1>
INPUTMC | 1 | 1 | 13
EQ | 2 | 
   new_reg<1> := registers<1>;	// (1 pt, 1 inp)
   new_reg<1>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 1 | 13 | registers<1>_MC
ATTRIBUTES | 2155905796 | 0
OUTPUTMC | 1 | 1 | 15
INPUTS | 1 | new_reg<2>
INPUTMC | 1 | 1 | 14
EQ | 2 | 
   registers<1> := new_reg<2>;	// (1 pt, 1 inp)
   registers<1>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 1 | 14 | new_reg<2>_MC
ATTRIBUTES | 2155905792 | 0
OUTPUTMC | 1 | 1 | 13
INPUTS | 1 | registers<2>
INPUTMC | 1 | 1 | 12
EQ | 2 | 
   new_reg<2> := registers<2>;	// (1 pt, 1 inp)
   new_reg<2>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 1 | 12 | registers<2>_MC
ATTRIBUTES | 2155905792 | 0
OUTPUTMC | 1 | 1 | 14
INPUTS | 1 | seq<9>
INPUTMC | 1 | 0 | 14
EQ | 2 | 
   registers<2> := seq<9>;	// (1 pt, 1 inp)
   registers<2>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 14 | seq<9>_MC
ATTRIBUTES | 2156167938 | 0
OUTPUTMC | 1 | 1 | 12
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<9> := registers<3>;	// (1 pt, 1 inp)
   seq<9>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 1 | seq<11>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<11> := registers<3>;	// (1 pt, 1 inp)
   seq<11>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 2 | seq<12>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<12> := registers<3>;	// (1 pt, 1 inp)
   seq<12>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 3 | seq<13>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<13> := registers<3>;	// (1 pt, 1 inp)
   seq<13>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 4 | seq<14>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<14> := registers<3>;	// (1 pt, 1 inp)
   seq<14>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 5 | seq<15>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<15> := registers<3>;	// (1 pt, 1 inp)
   seq<15>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 6 | seq<1>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<1> := registers<3>;	// (1 pt, 1 inp)
   seq<1>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 7 | seq<2>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<2> := registers<3>;	// (1 pt, 1 inp)
   seq<2>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 8 | seq<3>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<3> := registers<3>;	// (1 pt, 1 inp)
   seq<3>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 9 | seq<4>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<4> := registers<3>;	// (1 pt, 1 inp)
   seq<4>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 10 | seq<5>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<5> := registers<3>;	// (1 pt, 1 inp)
   seq<5>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 11 | seq<6>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<6> := registers<3>;	// (1 pt, 1 inp)
   seq<6>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 12 | seq<7>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<7> := registers<3>;	// (1 pt, 1 inp)
   seq<7>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

MACROCELL | 0 | 13 | seq<8>_MC
ATTRIBUTES | 8684290 | 0
INPUTS | 1 | registers<3>
INPUTMC | 1 | 1 | 11
EQ | 2 | 
   seq<8> := registers<3>;	// (1 pt, 1 inp)
   seq<8>.CLK  =  clk;	// GCK	(0 pt, 0 inp)
GLOBALS | 1 | 2 | clk

PIN | clk | 4096 | 0 | LVCMOS18 | 10 | 22 | 0 | 14 | 1 | 12 | 1 | 14 | 1 | 13 | 1 | 15 | 1 | 10 | 0 | 15 | 1 | 11 | 0 | 0 | 0 | 1 | 0 | 2 | 0 | 3 | 0 | 4 | 0 | 5 | 0 | 6 | 0 | 7 | 0 | 8 | 0 | 9 | 0 | 10 | 0 | 11 | 0 | 12 | 0 | 13
PIN | seq<10> | 536871040 | 0 | LVCMOS18 | 5
PIN | seq<11> | 536871040 | 0 | LVCMOS18 | 4
PIN | seq<12> | 536871040 | 0 | LVCMOS18 | 3
PIN | seq<13> | 536871040 | 0 | LVCMOS18 | 1
PIN | seq<14> | 536871040 | 0 | LVCMOS18 | 44
PIN | seq<15> | 536871040 | 0 | LVCMOS18 | 43
PIN | seq<1> | 536871040 | 0 | LVCMOS18 | 42
PIN | seq<2> | 536871040 | 0 | LVCMOS18 | 41
PIN | seq<3> | 536871040 | 0 | LVCMOS18 | 40
PIN | seq<4> | 536871040 | 0 | LVCMOS18 | 39
PIN | seq<5> | 536871040 | 0 | LVCMOS18 | 38
PIN | seq<6> | 536871040 | 0 | LVCMOS18 | 34
PIN | seq<7> | 536871040 | 0 | LVCMOS18 | 33
PIN | seq<8> | 536871040 | 0 | LVCMOS18 | 32
PIN | seq<9> | 536871040 | 0 | LVCMOS18 | 31