pn_timesim.vhd

用VHDL语言编写的PN码产生程序

  registers_2_MC_REG : X_FF
    port map (
      I => registers_2_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => registers_2_MC_Q
    );
  registers_2_MC_D_31 : X_XOR2
    port map (
      I0 => registers_2_MC_D1,
      I1 => registers_2_MC_D2,
      O => registers_2_MC_D
    );
  registers_2_MC_D1_32 : X_AND2
    port map (
      I0 => seq_9_MC_UIM,
      I1 => seq_9_MC_UIM,
      O => registers_2_MC_D1
    );
  registers_2_MC_D2_33 : X_ZERO
    port map (
      O => registers_2_MC_D2
    );
  seq_9_MC_Q_34 : X_BUF
    port map (
      I => seq_9_MC_Q_tsimrenamed_net_Q,
      O => seq_9_MC_Q
    );
  seq_9_MC_UIM_35 : X_BUF
    port map (
      I => seq_9_MC_Q_tsimrenamed_net_Q,
      O => seq_9_MC_UIM
    );
  seq_9_MC_REG : X_FF
    port map (
      I => seq_9_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_9_MC_Q_tsimrenamed_net_Q
    );
  seq_9_MC_D_36 : X_XOR2
    port map (
      I0 => seq_9_MC_D1,
      I1 => seq_9_MC_D2,
      O => seq_9_MC_D
    );
  seq_9_MC_D1_37 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_9_MC_D1
    );
  seq_9_MC_D2_38 : X_ZERO
    port map (
      O => seq_9_MC_D2
    );
  seq_11_MC_Q_39 : X_BUF
    port map (
      I => seq_11_MC_Q_tsimrenamed_net_Q,
      O => seq_11_MC_Q
    );
  seq_11_MC_REG : X_FF
    port map (
      I => seq_11_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_11_MC_Q_tsimrenamed_net_Q
    );
  seq_11_MC_D_40 : X_XOR2
    port map (
      I0 => seq_11_MC_D1,
      I1 => seq_11_MC_D2,
      O => seq_11_MC_D
    );
  seq_11_MC_D1_41 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_11_MC_D1
    );
  seq_11_MC_D2_42 : X_ZERO
    port map (
      O => seq_11_MC_D2
    );
  seq_12_MC_Q_43 : X_BUF
    port map (
      I => seq_12_MC_Q_tsimrenamed_net_Q,
      O => seq_12_MC_Q
    );
  seq_12_MC_REG : X_FF
    port map (
      I => seq_12_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_12_MC_Q_tsimrenamed_net_Q
    );
  seq_12_MC_D_44 : X_XOR2
    port map (
      I0 => seq_12_MC_D1,
      I1 => seq_12_MC_D2,
      O => seq_12_MC_D
    );
  seq_12_MC_D1_45 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_12_MC_D1
    );
  seq_12_MC_D2_46 : X_ZERO
    port map (
      O => seq_12_MC_D2
    );
  seq_13_MC_Q_47 : X_BUF
    port map (
      I => seq_13_MC_Q_tsimrenamed_net_Q,
      O => seq_13_MC_Q
    );
  seq_13_MC_REG : X_FF
    port map (
      I => seq_13_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_13_MC_Q_tsimrenamed_net_Q
    );
  seq_13_MC_D_48 : X_XOR2
    port map (
      I0 => seq_13_MC_D1,
      I1 => seq_13_MC_D2,
      O => seq_13_MC_D
    );
  seq_13_MC_D1_49 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_13_MC_D1
    );
  seq_13_MC_D2_50 : X_ZERO
    port map (
      O => seq_13_MC_D2
    );
  seq_14_MC_Q_51 : X_BUF
    port map (
      I => seq_14_MC_Q_tsimrenamed_net_Q,
      O => seq_14_MC_Q
    );
  seq_14_MC_REG : X_FF
    port map (
      I => seq_14_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_14_MC_Q_tsimrenamed_net_Q
    );
  seq_14_MC_D_52 : X_XOR2
    port map (
      I0 => seq_14_MC_D1,
      I1 => seq_14_MC_D2,
      O => seq_14_MC_D
    );
  seq_14_MC_D1_53 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_14_MC_D1
    );
  seq_14_MC_D2_54 : X_ZERO
    port map (
      O => seq_14_MC_D2
    );
  seq_15_MC_Q_55 : X_BUF
    port map (
      I => seq_15_MC_Q_tsimrenamed_net_Q,
      O => seq_15_MC_Q
    );
  seq_15_MC_REG : X_FF
    port map (
      I => seq_15_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_15_MC_Q_tsimrenamed_net_Q
    );
  seq_15_MC_D_56 : X_XOR2
    port map (
      I0 => seq_15_MC_D1,
      I1 => seq_15_MC_D2,
      O => seq_15_MC_D
    );
  seq_15_MC_D1_57 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_15_MC_D1
    );
  seq_15_MC_D2_58 : X_ZERO
    port map (
      O => seq_15_MC_D2
    );
  seq_1_MC_Q_59 : X_BUF
    port map (
      I => seq_1_MC_Q_tsimrenamed_net_Q,
      O => seq_1_MC_Q
    );
  seq_1_MC_REG : X_FF
    port map (
      I => seq_1_MC_D,
      CE => Vcc,
      CLK => FOOBAR2_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_1_MC_Q_tsimrenamed_net_Q
    );
  seq_1_MC_D_60 : X_XOR2
    port map (
      I0 => seq_1_MC_D1,
      I1 => seq_1_MC_D2,
      O => seq_1_MC_D
    );
  seq_1_MC_D1_61 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_1_MC_D1
    );
  seq_1_MC_D2_62 : X_ZERO
    port map (
      O => seq_1_MC_D2
    );
  seq_2_MC_Q_63 : X_BUF
    port map (
      I => seq_2_MC_Q_tsimrenamed_net_Q,
      O => seq_2_MC_Q
    );
  seq_2_MC_REG : X_FF
    port map (
      I => seq_2_MC_D,
      CE => Vcc,
      CLK => FOOBAR2_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_2_MC_Q_tsimrenamed_net_Q
    );
  seq_2_MC_D_64 : X_XOR2
    port map (
      I0 => seq_2_MC_D1,
      I1 => seq_2_MC_D2,
      O => seq_2_MC_D
    );
  seq_2_MC_D1_65 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_2_MC_D1
    );
  seq_2_MC_D2_66 : X_ZERO
    port map (
      O => seq_2_MC_D2
    );
  seq_3_MC_Q_67 : X_BUF
    port map (
      I => seq_3_MC_Q_tsimrenamed_net_Q,
      O => seq_3_MC_Q
    );
  seq_3_MC_REG : X_FF
    port map (
      I => seq_3_MC_D,
      CE => Vcc,
      CLK => FOOBAR2_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_3_MC_Q_tsimrenamed_net_Q
    );
  seq_3_MC_D_68 : X_XOR2
    port map (
      I0 => seq_3_MC_D1,
      I1 => seq_3_MC_D2,
      O => seq_3_MC_D
    );
  seq_3_MC_D1_69 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_3_MC_D1
    );
  seq_3_MC_D2_70 : X_ZERO
    port map (
      O => seq_3_MC_D2
    );
  seq_4_MC_Q_71 : X_BUF
    port map (
      I => seq_4_MC_Q_tsimrenamed_net_Q,
      O => seq_4_MC_Q
    );
  seq_4_MC_REG : X_FF
    port map (
      I => seq_4_MC_D,
      CE => Vcc,
      CLK => FOOBAR2_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_4_MC_Q_tsimrenamed_net_Q
    );
  seq_4_MC_D_72 : X_XOR2
    port map (
      I0 => seq_4_MC_D1,
      I1 => seq_4_MC_D2,
      O => seq_4_MC_D
    );
  seq_4_MC_D1_73 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_4_MC_D1
    );
  seq_4_MC_D2_74 : X_ZERO
    port map (
      O => seq_4_MC_D2
    );
  seq_5_MC_Q_75 : X_BUF
    port map (
      I => seq_5_MC_Q_tsimrenamed_net_Q,
      O => seq_5_MC_Q
    );
  seq_5_MC_REG : X_FF
    port map (
      I => seq_5_MC_D,
      CE => Vcc,
      CLK => FOOBAR2_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_5_MC_Q_tsimrenamed_net_Q
    );
  seq_5_MC_D_76 : X_XOR2
    port map (
      I0 => seq_5_MC_D1,
      I1 => seq_5_MC_D2,
      O => seq_5_MC_D
    );
  seq_5_MC_D1_77 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_5_MC_D1
    );
  seq_5_MC_D2_78 : X_ZERO
    port map (
      O => seq_5_MC_D2
    );
  seq_6_MC_Q_79 : X_BUF
    port map (
      I => seq_6_MC_Q_tsimrenamed_net_Q,
      O => seq_6_MC_Q
    );
  seq_6_MC_REG : X_FF
    port map (
      I => seq_6_MC_D,
      CE => Vcc,
      CLK => FOOBAR2_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_6_MC_Q_tsimrenamed_net_Q
    );
  seq_6_MC_D_80 : X_XOR2
    port map (
      I0 => seq_6_MC_D1,
      I1 => seq_6_MC_D2,
      O => seq_6_MC_D
    );
  seq_6_MC_D1_81 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_6_MC_D1
    );
  seq_6_MC_D2_82 : X_ZERO
    port map (
      O => seq_6_MC_D2
    );
  seq_7_MC_Q_83 : X_BUF
    port map (
      I => seq_7_MC_Q_tsimrenamed_net_Q,
      O => seq_7_MC_Q
    );
  seq_7_MC_REG : X_FF
    port map (
      I => seq_7_MC_D,
      CE => Vcc,
      CLK => FOOBAR2_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_7_MC_Q_tsimrenamed_net_Q
    );
  seq_7_MC_D_84 : X_XOR2
    port map (
      I0 => seq_7_MC_D1,
      I1 => seq_7_MC_D2,
      O => seq_7_MC_D
    );
  seq_7_MC_D1_85 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_7_MC_D1
    );
  seq_7_MC_D2_86 : X_ZERO
    port map (
      O => seq_7_MC_D2
    );
  seq_8_MC_Q_87 : X_BUF
    port map (
      I => seq_8_MC_Q_tsimrenamed_net_Q,
      O => seq_8_MC_Q
    );
  seq_8_MC_REG : X_FF
    port map (
      I => seq_8_MC_D,
      CE => Vcc,
      CLK => FOOBAR2_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_8_MC_Q_tsimrenamed_net_Q
    );
  seq_8_MC_D_88 : X_XOR2
    port map (
      I0 => seq_8_MC_D1,
      I1 => seq_8_MC_D2,
      O => seq_8_MC_D
    );
  seq_8_MC_D1_89 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_8_MC_D1
    );
  seq_8_MC_D2_90 : X_ZERO
    port map (
      O => seq_8_MC_D2
    );
  FOOBAR1_ctinst_4_91 : X_AND2
    port map (
      I0 => clk_II_UIM,
      I1 => clk_II_UIM,
      O => FOOBAR1_ctinst_4
    );
  FOOBAR2_ctinst_4_92 : X_AND2
    port map (
      I0 => clk_II_UIM,
      I1 => clk_II_UIM,
      O => FOOBAR2_ctinst_4
    );
  NlwInverterBlock_new_reg_4_MC_D2_PT_0_IN1 : X_INV
    port map (
      I => registers_0,
      O => NlwInverterSignal_new_reg_4_MC_D2_PT_0_IN1
    );
  NlwInverterBlock_new_reg_4_MC_D2_PT_1_IN0 : X_INV
    port map (
      I => registers(3),
      O => NlwInverterSignal_new_reg_4_MC_D2_PT_1_IN0
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => PRLD);

end Structure;