pn_timesim.vhd

用VHDL语言编写的PN码产生程序

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: pn_timesim.vhd
-- /___/   /\     Timestamp: Tue Apr 10 22:33:00 2007
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim pn.nga pn_timesim.vhd 
-- Device: XA2C32A-6-VQ44 (Speed File: Version 10.0 Advance Product Specification)
-- Design Name: pn.nga
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity pn is
  port (
    clk : in STD_LOGIC := 'X'; 
    seq : out STD_LOGIC_VECTOR ( 1 to 15 ) 
  );
end pn;

architecture Structure of pn is
  signal clk_II_UIM : STD_LOGIC; 
  signal seq_10_MC_Q : STD_LOGIC; 
  signal seq_11_MC_Q : STD_LOGIC; 
  signal seq_12_MC_Q : STD_LOGIC; 
  signal seq_13_MC_Q : STD_LOGIC; 
  signal seq_14_MC_Q : STD_LOGIC; 
  signal seq_15_MC_Q : STD_LOGIC; 
  signal seq_1_MC_Q : STD_LOGIC; 
  signal seq_2_MC_Q : STD_LOGIC; 
  signal seq_3_MC_Q : STD_LOGIC; 
  signal seq_4_MC_Q : STD_LOGIC; 
  signal seq_5_MC_Q : STD_LOGIC; 
  signal seq_6_MC_Q : STD_LOGIC; 
  signal seq_7_MC_Q : STD_LOGIC; 
  signal seq_8_MC_Q : STD_LOGIC; 
  signal seq_9_MC_Q : STD_LOGIC; 
  signal seq_10_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_10_MC_D : STD_LOGIC; 
  signal FOOBAR1_ctinst_4 : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal seq_10_MC_D1 : STD_LOGIC; 
  signal seq_10_MC_D2 : STD_LOGIC; 
  signal registers_3_MC_Q : STD_LOGIC; 
  signal registers_3_MC_D : STD_LOGIC; 
  signal registers_3_MC_D1 : STD_LOGIC; 
  signal registers_3_MC_D2 : STD_LOGIC; 
  signal new_reg_4_Q : STD_LOGIC; 
  signal new_reg_4_MC_Q : STD_LOGIC; 
  signal new_reg_4_MC_D : STD_LOGIC; 
  signal new_reg_4_MC_D1 : STD_LOGIC; 
  signal new_reg_4_MC_D2 : STD_LOGIC; 
  signal registers_0 : STD_LOGIC; 
  signal new_reg_4_MC_D2_PT_0 : STD_LOGIC; 
  signal new_reg_4_MC_D2_PT_1 : STD_LOGIC; 
  signal registers_0_MC_Q : STD_LOGIC; 
  signal registers_0_MC_D : STD_LOGIC; 
  signal registers_0_MC_D1 : STD_LOGIC; 
  signal registers_0_MC_D2 : STD_LOGIC; 
  signal new_reg_1_Q : STD_LOGIC; 
  signal new_reg_1_MC_Q : STD_LOGIC; 
  signal new_reg_1_MC_D : STD_LOGIC; 
  signal new_reg_1_MC_D1 : STD_LOGIC; 
  signal new_reg_1_MC_D2 : STD_LOGIC; 
  signal registers_1_MC_Q : STD_LOGIC; 
  signal registers_1_MC_D : STD_LOGIC; 
  signal registers_1_MC_D1 : STD_LOGIC; 
  signal registers_1_MC_D2 : STD_LOGIC; 
  signal new_reg_2_Q : STD_LOGIC; 
  signal new_reg_2_MC_Q : STD_LOGIC; 
  signal new_reg_2_MC_D : STD_LOGIC; 
  signal new_reg_2_MC_D1 : STD_LOGIC; 
  signal new_reg_2_MC_D2 : STD_LOGIC; 
  signal registers_2_MC_Q : STD_LOGIC; 
  signal registers_2_MC_D : STD_LOGIC; 
  signal registers_2_MC_D1 : STD_LOGIC; 
  signal registers_2_MC_D2 : STD_LOGIC; 
  signal seq_9_MC_UIM : STD_LOGIC; 
  signal seq_9_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_9_MC_D : STD_LOGIC; 
  signal seq_9_MC_D1 : STD_LOGIC; 
  signal seq_9_MC_D2 : STD_LOGIC; 
  signal seq_11_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_11_MC_D : STD_LOGIC; 
  signal seq_11_MC_D1 : STD_LOGIC; 
  signal seq_11_MC_D2 : STD_LOGIC; 
  signal seq_12_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_12_MC_D : STD_LOGIC; 
  signal seq_12_MC_D1 : STD_LOGIC; 
  signal seq_12_MC_D2 : STD_LOGIC; 
  signal seq_13_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_13_MC_D : STD_LOGIC; 
  signal seq_13_MC_D1 : STD_LOGIC; 
  signal seq_13_MC_D2 : STD_LOGIC; 
  signal seq_14_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_14_MC_D : STD_LOGIC; 
  signal seq_14_MC_D1 : STD_LOGIC; 
  signal seq_14_MC_D2 : STD_LOGIC; 
  signal seq_15_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_15_MC_D : STD_LOGIC; 
  signal seq_15_MC_D1 : STD_LOGIC; 
  signal seq_15_MC_D2 : STD_LOGIC; 
  signal seq_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_1_MC_D : STD_LOGIC; 
  signal FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal seq_1_MC_D1 : STD_LOGIC; 
  signal seq_1_MC_D2 : STD_LOGIC; 
  signal seq_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_2_MC_D : STD_LOGIC; 
  signal seq_2_MC_D1 : STD_LOGIC; 
  signal seq_2_MC_D2 : STD_LOGIC; 
  signal seq_3_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_3_MC_D : STD_LOGIC; 
  signal seq_3_MC_D1 : STD_LOGIC; 
  signal seq_3_MC_D2 : STD_LOGIC; 
  signal seq_4_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_4_MC_D : STD_LOGIC; 
  signal seq_4_MC_D1 : STD_LOGIC; 
  signal seq_4_MC_D2 : STD_LOGIC; 
  signal seq_5_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_5_MC_D : STD_LOGIC; 
  signal seq_5_MC_D1 : STD_LOGIC; 
  signal seq_5_MC_D2 : STD_LOGIC; 
  signal seq_6_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_6_MC_D : STD_LOGIC; 
  signal seq_6_MC_D1 : STD_LOGIC; 
  signal seq_6_MC_D2 : STD_LOGIC; 
  signal seq_7_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_7_MC_D : STD_LOGIC; 
  signal seq_7_MC_D1 : STD_LOGIC; 
  signal seq_7_MC_D2 : STD_LOGIC; 
  signal seq_8_MC_Q_tsimrenamed_net_Q : STD_LOGIC; 
  signal seq_8_MC_D : STD_LOGIC; 
  signal seq_8_MC_D1 : STD_LOGIC; 
  signal seq_8_MC_D2 : STD_LOGIC; 
  signal NlwInverterSignal_new_reg_4_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_new_reg_4_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal registers : STD_LOGIC_VECTOR ( 3 downto 1 ); 
begin
  clk_II_UIM_0 : X_BUF
    port map (
      I => clk,
      O => clk_II_UIM
    );
  seq_10_Q : X_BUF
    port map (
      I => seq_10_MC_Q,
      O => seq(10)
    );
  seq_11_Q : X_BUF
    port map (
      I => seq_11_MC_Q,
      O => seq(11)
    );
  seq_12_Q : X_BUF
    port map (
      I => seq_12_MC_Q,
      O => seq(12)
    );
  seq_13_Q : X_BUF
    port map (
      I => seq_13_MC_Q,
      O => seq(13)
    );
  seq_14_Q : X_BUF
    port map (
      I => seq_14_MC_Q,
      O => seq(14)
    );
  seq_15_Q : X_BUF
    port map (
      I => seq_15_MC_Q,
      O => seq(15)
    );
  seq_1_Q : X_BUF
    port map (
      I => seq_1_MC_Q,
      O => seq(1)
    );
  seq_2_Q : X_BUF
    port map (
      I => seq_2_MC_Q,
      O => seq(2)
    );
  seq_3_Q : X_BUF
    port map (
      I => seq_3_MC_Q,
      O => seq(3)
    );
  seq_4_Q : X_BUF
    port map (
      I => seq_4_MC_Q,
      O => seq(4)
    );
  seq_5_Q : X_BUF
    port map (
      I => seq_5_MC_Q,
      O => seq(5)
    );
  seq_6_Q : X_BUF
    port map (
      I => seq_6_MC_Q,
      O => seq(6)
    );
  seq_7_Q : X_BUF
    port map (
      I => seq_7_MC_Q,
      O => seq(7)
    );
  seq_8_Q : X_BUF
    port map (
      I => seq_8_MC_Q,
      O => seq(8)
    );
  seq_9_Q : X_BUF
    port map (
      I => seq_9_MC_Q,
      O => seq(9)
    );
  seq_10_MC_Q_1 : X_BUF
    port map (
      I => seq_10_MC_Q_tsimrenamed_net_Q,
      O => seq_10_MC_Q
    );
  seq_10_MC_REG : X_FF
    port map (
      I => seq_10_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => seq_10_MC_Q_tsimrenamed_net_Q
    );
  Gnd_2 : X_ZERO
    port map (
      O => Gnd
    );
  Vcc_3 : X_ONE
    port map (
      O => Vcc
    );
  seq_10_MC_D_4 : X_XOR2
    port map (
      I0 => seq_10_MC_D1,
      I1 => seq_10_MC_D2,
      O => seq_10_MC_D
    );
  seq_10_MC_D1_5 : X_AND2
    port map (
      I0 => registers(3),
      I1 => registers(3),
      O => seq_10_MC_D1
    );
  seq_10_MC_D2_6 : X_ZERO
    port map (
      O => seq_10_MC_D2
    );
  registers_3_Q : X_BUF
    port map (
      I => registers_3_MC_Q,
      O => registers(3)
    );
  registers_3_MC_REG : X_FF
    port map (
      I => registers_3_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => PRLD,
      RST => Gnd,
      O => registers_3_MC_Q
    );
  registers_3_MC_D_7 : X_XOR2
    port map (
      I0 => registers_3_MC_D1,
      I1 => registers_3_MC_D2,
      O => registers_3_MC_D
    );
  registers_3_MC_D1_8 : X_AND2
    port map (
      I0 => new_reg_4_Q,
      I1 => new_reg_4_Q,
      O => registers_3_MC_D1
    );
  registers_3_MC_D2_9 : X_ZERO
    port map (
      O => registers_3_MC_D2
    );
  new_reg_4_Q_10 : X_BUF
    port map (
      I => new_reg_4_MC_Q,
      O => new_reg_4_Q
    );
  new_reg_4_MC_REG : X_FF
    port map (
      I => new_reg_4_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => new_reg_4_MC_Q
    );
  new_reg_4_MC_D_11 : X_XOR2
    port map (
      I0 => new_reg_4_MC_D1,
      I1 => new_reg_4_MC_D2,
      O => new_reg_4_MC_D
    );
  new_reg_4_MC_D1_12 : X_ZERO
    port map (
      O => new_reg_4_MC_D1
    );
  new_reg_4_MC_D2_PT_0_13 : X_AND2
    port map (
      I0 => registers(3),
      I1 => NlwInverterSignal_new_reg_4_MC_D2_PT_0_IN1,
      O => new_reg_4_MC_D2_PT_0
    );
  new_reg_4_MC_D2_PT_1_14 : X_AND2
    port map (
      I0 => NlwInverterSignal_new_reg_4_MC_D2_PT_1_IN0,
      I1 => registers_0,
      O => new_reg_4_MC_D2_PT_1
    );
  new_reg_4_MC_D2_15 : X_OR2
    port map (
      I0 => new_reg_4_MC_D2_PT_0,
      I1 => new_reg_4_MC_D2_PT_1,
      O => new_reg_4_MC_D2
    );
  registers_0_16 : X_BUF
    port map (
      I => registers_0_MC_Q,
      O => registers_0
    );
  registers_0_MC_REG : X_FF
    port map (
      I => registers_0_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => registers_0_MC_Q
    );
  registers_0_MC_D_17 : X_XOR2
    port map (
      I0 => registers_0_MC_D1,
      I1 => registers_0_MC_D2,
      O => registers_0_MC_D
    );
  registers_0_MC_D1_18 : X_AND2
    port map (
      I0 => new_reg_1_Q,
      I1 => new_reg_1_Q,
      O => registers_0_MC_D1
    );
  registers_0_MC_D2_19 : X_ZERO
    port map (
      O => registers_0_MC_D2
    );
  new_reg_1_Q_20 : X_BUF
    port map (
      I => new_reg_1_MC_Q,
      O => new_reg_1_Q
    );
  new_reg_1_MC_REG : X_FF
    port map (
      I => new_reg_1_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => new_reg_1_MC_Q
    );
  new_reg_1_MC_D_21 : X_XOR2
    port map (
      I0 => new_reg_1_MC_D1,
      I1 => new_reg_1_MC_D2,
      O => new_reg_1_MC_D
    );
  new_reg_1_MC_D1_22 : X_AND2
    port map (
      I0 => registers(1),
      I1 => registers(1),
      O => new_reg_1_MC_D1
    );
  new_reg_1_MC_D2_23 : X_ZERO
    port map (
      O => new_reg_1_MC_D2
    );
  registers_1_Q : X_BUF
    port map (
      I => registers_1_MC_Q,
      O => registers(1)
    );
  registers_1_MC_REG : X_FF
    port map (
      I => registers_1_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => registers_1_MC_Q
    );
  registers_1_MC_D_24 : X_XOR2
    port map (
      I0 => registers_1_MC_D1,
      I1 => registers_1_MC_D2,
      O => registers_1_MC_D
    );
  registers_1_MC_D1_25 : X_AND2
    port map (
      I0 => new_reg_2_Q,
      I1 => new_reg_2_Q,
      O => registers_1_MC_D1
    );
  registers_1_MC_D2_26 : X_ZERO
    port map (
      O => registers_1_MC_D2
    );
  new_reg_2_Q_27 : X_BUF
    port map (
      I => new_reg_2_MC_Q,
      O => new_reg_2_Q
    );
  new_reg_2_MC_REG : X_FF
    port map (
      I => new_reg_2_MC_D,
      CE => Vcc,
      CLK => FOOBAR1_ctinst_4,
      SET => Gnd,
      RST => PRLD,
      O => new_reg_2_MC_Q
    );
  new_reg_2_MC_D_28 : X_XOR2
    port map (
      I0 => new_reg_2_MC_D1,
      I1 => new_reg_2_MC_D2,
      O => new_reg_2_MC_D
    );
  new_reg_2_MC_D1_29 : X_AND2
    port map (
      I0 => registers(2),
      I1 => registers(2),
      O => new_reg_2_MC_D1
    );
  new_reg_2_MC_D2_30 : X_ZERO
    port map (
      O => new_reg_2_MC_D2
    );
  registers_2_Q : X_BUF
    port map (
      I => registers_2_MC_Q,
      O => registers(2)
    );