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tdtfi(vhdl) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Extracting independent architecture files...caution: filename not matched: andcaution: filename not matched: settings/wq/desktop/wq/newcaution: filename not matched: folder/pn/pn_html/fitRelease 7.1i - ngdbuild H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc pn.ucf -p acr2 pn.ngc pn.ngd Reading NGO file 'C:/Documents and Settings/wq/Desktop/wq/New Folder/pn/pn.ngc'...Applying constraints in "pn.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "pn.ngd" ...Writing NGDBUILD log file "pn.bld"...NGDBUILD done.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Extracting independent architecture files...caution: filename not matched: andcaution: filename not matched: settings/wq/desktop/wq/newcaution: filename not matched: folder/pn/pn_html/fitRelease 7.1i - ngdbuild H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc pn.ucf -p acr2 pn.ngc pn.ngd Reading NGO file 'C:/Documents and Settings/wq/Desktop/wq/New Folder/pn/pn.ngc'...Applying constraints in "pn.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "pn.ngd" ...Writing NGDBUILD log file "pn.bld"...NGDBUILD done.
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Started process "Fit".Release 7.1i - CPLD Optimizer/Partitioner H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XA2C32A-6-VQ44.Re-checking device resources ......Synthesizing and Optimizing........................................................................................................................o.......Fitting........oDesign pn has been optimized and fit into device XA2C32A-6-VQ44.pn.xml:2: I/O warning : failed to load external entity "NULL"ent SYSTEM "file:///D:/Program Files/Xilinx ISE 7.1i/acr2/data/xmlReportxbr.dtd" ^pn.xml:2: I/O warning : failed to load external entity "NULL"ent SYSTEM "file:///D:/Program Files/Xilinx ISE 7.1i/acr2/data/xmlReportxbr.dtd" ^pn.xml:2: I/O warning : failed to load external entity "NULL"ent SYSTEM "file:///D:/Program Files/Xilinx ISE 7.1i/acr2/data/xmlReportxbr.dtd" ^pn.xml:2: I/O warning : failed to load external entity "NULL"ent SYSTEM "file:///D:/Program Files/Xilinx ISE 7.1i/acr2/data/xmlReportxbr.dtd" ^
Started process "Generate Post-Fit Simulation Model".Release 7.1i - CPLD Timing Simulation Interface H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Creating NGA for simulation.Speed File: Version 10.0 Advance Product Specification
Release 7.1i - netgen H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim pn.ngapn_timesim.vhd Reading design 'pn.nga' ...Flattening design ...Processing design ... Preping design's networks ... Preping design's macros ...Writing VHDL netlist 'pn_timesim.vhd' ...Writing VHDL SDF file 'pn_timesim.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM library for correct compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 44048 kilobytesCreated netgen log file 'pn_timesim.nlf'.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/Documents and Settings/wq/Desktop/wq/New Folder/pn/pn.vhd" in Library work.Entity <pn> compiled.Entity <pn> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <pn> (Architecture <behavioral>).Entity <pn> analyzed. Unit <pn> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <pn>. Related source file is "C:/Documents and Settings/wq/Desktop/wq/New Folder/pn/pn.vhd".WARNING:Xst:1780 - Signal <n> is never used or assigned.WARNING:Xst:653 - Signal <connections<4>> is used but never assigned. Tied to value 1.WARNING:Xst:1780 - Signal <connections<3:2>> is never used or assigned.WARNING:Xst:653 - Signal <connections<1>> is used but never assigned. Tied to value 1. Register <seq<11>> equivalent to <seq<10>> has been removed Register <seq<12>> equivalent to <seq<10>> has been removed Register <seq<13>> equivalent to <seq<10>> has been removed Register <seq<14>> equivalent to <seq<10>> has been removed Register <seq<15>> equivalent to <seq<10>> has been removed Register <seq<1>> equivalent to <seq<10>> has been removed Register <seq<2>> equivalent to <seq<10>> has been removed Register <seq<3>> equivalent to <seq<10>> has been removed Register <seq<4>> equivalent to <seq<10>> has been removed Register <seq<5>> equivalent to <seq<10>> has been removed Register <seq<6>> equivalent to <seq<10>> has been removed Register <seq<7>> equivalent to <seq<10>> has been removed Register <new_reg<3>> equivalent to <seq<10>> has been removed Register <seq<8>> equivalent to <seq<10>> has been removed Register <seq<9>> equivalent to <seq<10>> has been removed Found 1-bit register for signal <seq<10>>. Found 1-bit xor2 for signal <$n0000> created at line 52. Found 1-bit register for signal <new_reg<4>>. Found 2-bit register for signal <new_reg<2:1>>. Found 4-bit register for signal <registers>. Summary: inferred 4 D-type flip-flop(s). inferred 1 Xor(s).Unit <pn> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 5 1-bit register : 4 4-bit register : 1# Xors : 1 1-bit xor2 : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <pn> ... implementation constraint: INIT=s : registers_1 implementation constraint: INIT=s : registers_3 implementation constraint: INIT=r : registers_2 implementation constraint: INIT=r : registers_0
Started process "Translate".Extracting independent architecture files...caution: filename not matched: andcaution: filename not matched: settings/wq/desktop/wq/newcaution: filename not matched: folder/pn/pn_html/fitRelease 7.1i - ngdbuild H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc pn.ucf -p acr2 pn.ngc pn.ngd Reading NGO file 'C:/Documents and Settings/wq/Desktop/wq/New Folder/pn/pn.ngc'...Applying constraints in "pn.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "pn.ngd" ...Writing NGDBUILD log file "pn.bld"...NGDBUILD done.
Started process "Fit".Release 7.1i - CPLD Optimizer/Partitioner H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XA2C32A-6-VQ44.Re-checking device resources ......Synthesizing and Optimizing........................................................................................................................o.......Fitting........oDesign pn has been optimized and fit into device XA2C32A-6-VQ44.pn.xml:2: I/O warning : failed to load external entity "NULL"ent SYSTEM "file:///D:/Program Files/Xilinx ISE 7.1i/acr2/data/xmlReportxbr.dtd" ^pn.xml:2: I/O warning : failed to load external entity "NULL"ent SYSTEM "file:///D:/Program Files/Xilinx ISE 7.1i/acr2/data/xmlReportxbr.dtd" ^pn.xml:2: I/O warning : failed to load external entity "NULL"ent SYSTEM "file:///D:/Program Files/Xilinx ISE 7.1i/acr2/data/xmlReportxbr.dtd" ^pn.xml:2: I/O warning : failed to load external entity "NULL"ent SYSTEM "file:///D:/Program Files/Xilinx ISE 7.1i/acr2/data/xmlReportxbr.dtd" ^
Started process "Generate Programming File".Release 7.1i - Programming File Generator H.38Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "C:/Documents and Settings/wq/Desktop/wq/New Folder/pn/pn.vhd" in Library work.Entity <pn> compiled.Entity <pn> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <pn> (Architecture <behavioral>).Entity <pn> analyzed. Unit <pn> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <pn>. Rel⌨️ 快捷键说明
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