pn.chk

用VHDL语言编写的PN码产生程序

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|  P a r t i t i o n    S u c c e e d  |
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0 Group(s)

GCLK0: 0=clk.p
----------------- B l o c k 0 ------------------
PLApt(17/56), Fanin(2/38), Clk(1/3), Bct(0/4), Pin(15/16), Mcell(16/16)
PLApts[17/53] 7 8 () () () () () () () () 2 () () 2 () () 2 () () 2 () () 2 () () 2 () () 2 () () 2 () () 2 
              () () 2 () () 2 () () 2 () () 2 () () 2 () () 2
Fanins[ 2] registers<3>.n registers_0.n
clk[1] clk 
CTC: 
CTR: 
CTS: 
CTE: 
vref: [0]
Signal[16] [seq<10>(45),seq<10>(38)] [seq<11>(46),seq<11>(37)] [seq<12>(47),seq<12>(36)]  
           [seq<13>(48),seq<13>(34)] [seq<14>(49),seq<14>(33)] [seq<15>(50),seq<15>(32)]  
           [seq<1>(51),seq<1>(31)] [seq<2>(52),seq<2>(30)] [seq<3>(53),seq<3>(29)] [seq<4>(54),seq<4>(28)]  
           [seq<5>(55),seq<5>(27)] [seq<6>(56),seq<6>(23)] [seq<7>(57),seq<7>(22)] [seq<8>(58),seq<8>(21)]  
           [seq<9>(59),seq<9>(20)] [new_reg<4>(60)] 
Signal[16] [ 0: seq<10>(45) seq<10>(38)  ][ 1: seq<11>(46) seq<11>(37)  ][ 2: seq<12>(47) seq<12>(36)  ][ 3:  
           seq<13>(48) seq<13>(34)  ][ 4: seq<14>(49) seq<14>(33)  ][ 5: seq<15>(50) seq<15>(32)  ][ 6:  
           seq<1>(51) seq<1>(31)  ][ 7: seq<2>(52) seq<2>(30)  ][ 8: seq<3>(53) seq<3>(29)  ][ 9: seq<4>(54)  
           seq<4>(28)  ][ 10: seq<5>(55) seq<5>(27)  ][ 11: seq<6>(56) seq<6>(23)  ][ 12: seq<7>(57)  
           seq<7>(22)  ][ 13: seq<8>(58) seq<8>(21)  ][ 14: seq<9>(59) seq<9>(20)  ][ 15: new_reg<4>(60)  
           (19)  ]
----------------- B l o c k 1 ------------------
PLApt(6/56), Fanin(6/38), Clk(1/3), Bct(0/4), Pin(1/16), Mcell(6/16)
PLApts[6/56] () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () () 
             () () () () () () () () 3 () () 9 () () 1 () () 4 () () 6 () () 5
Fanins[ 6] seq<9>.n new_reg<1>.n new_reg<2>.n new_reg<4>.n registers<1>.n registers<2>.n
clk[1] clk 
CTC: 
CTR: 
CTS: 
CTE: 
vref: [0]
Signal[ 7] [clk(43)] [new_reg<1>(76)] [new_reg<2>(75)] [registers<1>(74)] [registers<2>(73)]  
           [registers<3>(72)] [registers_0(71)] 
Signal[ 7] [ 0: (39)  ][ 1: (40)  ][ 2: (41)  ][ 3: (42)  ][ 4: clk(43)  ][ 5: (44)  ][ 6: (1)  ][ 7: (2)  ] 
           [ 8: (3)  ][ 9: (5)  ][ 10: registers_0(71) (6)  ][ 11: registers<3>(72) (8)  ][ 12:  
           registers<2>(73) (12)  ][ 13: registers<1>(74) (13)  ][ 14: new_reg<2>(75) (14)  ][ 15:  
           new_reg<1>(76) (16)  ]