pn.syr

用VHDL语言编写的PN码产生程序

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: pn.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "pn.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "pn"
Output Format                      : NGC
Target Device                      : xc4vfx12-12-sf363

---- Source Options
Top Module Name                    : pn
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 32
Number of Regional Clock Buffers   : Default
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : pn.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
use_dsp48                          : auto
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Auto
use_sync_set                       : Auto
use_sync_reset                     : Auto
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/nf/pn/pn.vhd" in Library work.
Architecture behavioral of Entity pn is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <pn> (Architecture <behavioral>).
Entity <pn> analyzed. Unit <pn> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pn>.
    Related source file is "D:/nf/pn/pn.vhd".
WARNING:Xst:653 - Signal <connections<4>> is used but never assigned. Tied to value 1.
WARNING:Xst:1780 - Signal <connections<3:2>> is never used or assigned.
WARNING:Xst:653 - Signal <connections<1>> is used but never assigned. Tied to value 1.
    Register <new_reg<3>> equivalent to <seq> has been removed
    Found 1-bit register for signal <seq>.
    Found 1-bit xor2 for signal <$n0002> created at line 56.
    Found 32-bit up counter for signal <cnt>.
    Found 1-bit register for signal <new_reg<4>>.
    Found 2-bit register for signal <new_reg<2:1>>.
    Found 4-bit register for signal <registers>.
    Summary:
	inferred   1 Counter(s).
	inferred   8 D-type flip-flop(s).
Unit <pn> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
 1-bit register                    : 4
 4-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <pn> ...
Loading device for application Rf_Device from file '4vfx12.nph' in environment D:/Program Files/Xilinx ISE 7.1i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pn, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : pn.ngr
Top Level Output File Name         : pn
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 3

Macro Statistics :
# Registers                        : 5
#      1-bit register              : 4
#      4-bit register              : 1

Cell Usage :
# BELS                             : 1
#      LUT2_L                      : 1
# FlipFlops/Latches                : 8
#      FDE                         : 8
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 2
#      IBUF                        : 1
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vfx12sf363-12 

 Number of Slices:                       5  out of   5472     0%  
 Number of Slice Flip Flops:             8  out of  10944     0%  
 Number of 4 input LUTs:                 1  out of  10944     0%  
 Number of bonded IOBs:                  3  out of    240     1%  
 Number of GCLKs:                        1  out of     32     3%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -12

   Minimum period: 1.285ns (Maximum Frequency: 777.968MHz)
   Minimum input arrival time before clock: 1.783ns
   Maximum output required time after clock: 3.935ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 1.285ns (frequency: 777.968MHz)
  Total number of paths / destination ports: 9 / 8
-------------------------------------------------------------------------
Delay:               1.285ns (Levels of Logic = 1)
  Source:            registers_1 (FF)
  Destination:       new_reg_4 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: registers_1 to new_reg_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.272   0.569  registers_1 (registers_1)
     LUT2_L:I0->LO         1   0.147   0.000  Mxor__n0002_Result1 (_n0002)
     FDE:D                     0.297          new_reg_4
    ----------------------------------------
    Total                      1.285ns (0.716ns logic, 0.569ns route)
                                       (55.7% logic, 44.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              1.783ns (Levels of Logic = 1)
  Source:            reset (PAD)
  Destination:       seq (FF)
  Destination Clock: clk rising

  Data Path: reset to seq
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.754   0.467  reset_IBUF (reset_IBUF)
     FDE:CE                    0.562          new_reg_1
    ----------------------------------------
    Total                      1.783ns (1.316ns logic, 0.467ns route)
                                       (73.8% logic, 26.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.935ns (Levels of Logic = 1)
  Source:            seq (FF)
  Destination:       seq (PAD)
  Source Clock:      clk rising

  Data Path: seq to seq
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.272   0.408  seq (seq_OBUF)
     OBUF:I->O                 3.255          seq_OBUF (seq)
    ----------------------------------------
    Total                      3.935ns (3.527ns logic, 0.408ns route)
                                       (89.6% logic, 10.4% route)

=========================================================================
CPU : 8.69 / 9.14 s | Elapsed : 8.00 / 9.00 s
 
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Total memory usage is 177912 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    0 (   0 filtered)