pn.vhd

来自「用VHDL语言编写的PN码产生程序」· VHDL 代码 · 共 70 行

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-- Company: 
-- Engineer:
--
-- Create Date:    14:36:59 03/29/07
-- Design Name:    
-- Module Name:    pn - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pn is
port(reset:in std_logic;
clk:in std_logic;
--connections:in std_logic_vector(4 downto 1):="1001";
seq:out std_logic
);
end pn;

architecture Behavioral of pn is
signal registers: std_logic_vector(4 downto 1):="1010";
signal new_reg: std_logic_vector(4 downto 1);
signal cnt:integer;
--signal n:integer range 1 to 15;
signal connections: std_logic_vector(4 downto 1):="1001";
--signal dataout:std_logic_vector(1 to 15);
begin

 process(clk,reset)
 begin
  
  if reset='0' then
	cnt<=0;
  	elsif clk'event and clk='1' then
   seq<=registers(4); 
  registers(3 downto 1)<=registers(4 downto 2);
  registers(4)<=((connections(1) and registers(1))xor(connections(4) and registers(4))); 
--  registers(4 downto 1)<=new_reg(4 downto 1);
  	if cnt=15 then
	cnt<=0;
	else cnt<=cnt+1;
	end if;
end if;

end process;


				 

end Behavioral;