📄 pn.cxt
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Nm CDATA #REQUIRED><!ELEMENT Or (OPort, IPort+)><!ATTLIST Or Nm CDATA #REQUIRED><!ELEMENT ClkMux (IPort, OPort)><!ATTLIST ClkMux Nm CDATA #REQUIRED Rate (1 | 2) #IMPLIED><!ELEMENT RMux (IPort)><!ATTLIST RMux Nm CDATA #REQUIRED><!ELEMENT OeMux (IPort)><!ATTLIST OeMux Nm CDATA #REQUIRED><!ELEMENT XorMux (IPort)><!ATTLIST XorMux Nm CDATA #REQUIRED><!ELEMENT FbMux (IPort)><!ATTLIST FbMux Nm CDATA #REQUIRED><!ELEMENT OutBuf (IPort, OPort, CntlPort*)><!ATTLIST OutBuf Nm CDATA #REQUIRED IOS (LVTTL | LVCMOS15 | LVCMOS18 | LVCMOS25 | LVCMOS33 | HSTL_I | SSTL2_I | SSTL3_I | STRIG) #REQUIRED><!ELEMENT DFlop (FlopPort+)><!ATTLIST DFlop Nm CDATA #REQUIRED><!ELEMENT FlopPort EMPTY><!ATTLIST FlopPort NNm CDATA #REQUIRED Port (D | CLK | Q | RST | PST | CE) #REQUIRED><!ELEMENT IPort EMPTY><!ATTLIST IPort NNm CDATA #REQUIRED><!ELEMENT OPort EMPTY><!ATTLIST OPort NNm CDATA #REQUIRED><!ELEMENT CntlPort EMPTY><!ATTLIST CntlPort NNm CDATA #REQUIRED>]>
<Document Date="Apr 11 10:41:26 2007" Device="XA2C32A-6VQ44" Module="pn" Version="2"><Net IoT="none" NNm="FB1_PT10" SNm="seq<10>_MC.D"/><Net IoT="none" NNm="FB1_PT13" SNm="FB1_PT13"/><Net IoT="none" NNm="FB1_PT22" SNm="FB1_PT22"/><Net IoT="none" NNm="FB1_PT31" SNm="FB1_PT31"/><Net IoT="none" NNm="FB1_PT40" SNm="FB1_PT40"/><Net IoT="none" NNm="FB2_PT40" SNm="registers_0_MC.D"/><Net IoT="none" NNm="FB1_PT16" SNm="FB1_PT16"/><Net IoT="none" NNm="FB1_PT25" SNm="FB1_PT25"/><Net IoT="none" NNm="FB1_PT34" SNm="FB1_PT34"/><Net IoT="none" NNm="FB1_PT43" SNm="FB1_PT43"/><Net IoT="none" NNm="FB1_PT52" SNm="FB1_PT52"/><Net IoT="out" Loc="FB1_1" NNm="seq<10>" SNm="seq<10>"/><Net IoT="none" NNm="FB2_PT43" SNm="registers<3>_MC.D"/><Net IoT="none" NNm="FB2_PT52" SNm="new_reg<2>_MC.D"/><Net IoT="out" Loc="FB1_2" NNm="seq<11>" SNm="seq<11>"/><Net IoT="out" Loc="FB1_3" NNm="seq<12>" SNm="seq<12>"/><Net IoT="none" NNm="FB1_PT19" SNm="FB1_PT19"/><Net IoT="none" NNm="FB1_PT28" SNm="FB1_PT28"/><Net IoT="none" NNm="FB1_PT37" SNm="FB1_PT37"/><Net IoT="none" NNm="FB1_PT46" SNm="FB1_PT46"/><Net IoT="out" Loc="FB1_4" NNm="seq<13>" SNm="seq<13>"/><Net IoT="none" NNm="FB2_PT46" SNm="registers<2>_MC.D"/><Net IoT="none" NNm="FB2_PT55" SNm="new_reg<1>_MC.D"/><Net IoT="out" Loc="FB1_5" NNm="seq<14>" SNm="seq<14>"/><Net IoT="out" Loc="FB1_6" NNm="seq<15>" SNm="seq<15>"/><Net IoT="none" NNm="FB1_PT49" SNm="FB1_PT49"/><Net IoT="none" NNm="FB2_PT49" SNm="registers<1>_MC.D"/><Net IoT="in" Loc="FB2_5" NNm="clk" SNm="clk" ClkT="G"/><Net IoT="none" NNm="FB1_7_Q" SNm="seq<1>_MC.Q"/><Net IoT="none" NNm="FB1_8_Q" SNm="seq<2>_MC.Q"/><Net IoT="none" NNm="FB1_9_Q" SNm="seq<3>_MC.Q"/><Net IoT="none" NNm="FB1_10_Q" SNm="seq<4>_MC.Q"/><Net IoT="none" NNm="FB1_11_Q" SNm="seq<5>_MC.Q"/><Net IoT="none" NNm="FB1_12_Q" SNm="seq<6>_MC.Q"/><Net IoT="none" NNm="FB2_11_Q" SNm="registers_0_MC.Q"/><Net IoT="none" NNm="FB1_13_Q" SNm="seq<7>_MC.Q"/><Net IoT="none" NNm="FB1_14_Q" SNm="seq<8>_MC.Q"/><Net IoT="none" NNm="FB1_15_Q" SNm="seq<9>_MC.UIM"/><Net IoT="none" NNm="FB1_1_MC_CLK" SNm="FB1_1_MC_CLK"/><Net IoT="none" NNm="FB1_2_MC_CLK" SNm="FB1_2_MC_CLK"/><Net IoT="none" NNm="FB1_3_MC_CLK" SNm="FB1_3_MC_CLK"/><Net IoT="none" NNm="FB1_4_MC_CLK" SNm="FB1_4_MC_CLK"/><Net IoT="none" NNm="FB1_5_MC_CLK" SNm="FB1_5_MC_CLK"/><Net IoT="none" NNm="FB1_6_MC_CLK" SNm="FB1_6_MC_CLK"/><Net IoT="none" NNm="FB1_7_MC_CLK" SNm="FB1_7_MC_CLK"/><Net IoT="none" NNm="FB1_8_MC_CLK" SNm="FB1_8_MC_CLK"/><Net IoT="none" NNm="FB1_9_MC_CLK" SNm="FB1_9_MC_CLK"/><Net IoT="none" NNm="FB2_5_I" SNm="clk_II/FCLK"/><Net IoT="none" NNm="FB1_16_OR" SNm="new_reg<4>_MC.D"/><Net IoT="none" NNm="FB2_14_Q" SNm="registers<1>_MC.Q"/><Net IoT="none" NNm="FB2_13_Q" SNm="registers<2>_MC.Q"/><Net IoT="none" NNm="FB2_12_Q" SNm="registers<3>_MC.Q"/><Net IoT="none" NNm="FB2_16_Q" SNm="new_reg<1>_MC.Q"/><Net IoT="none" NNm="FB1_1_Q" SNm="seq<10>_MC.Q"/><Net IoT="none" NNm="FB2_15_Q" SNm="new_reg<2>_MC.Q"/><Net IoT="none" NNm="FB1_2_Q" SNm="seq<11>_MC.Q"/><Net IoT="none" NNm="FB1_3_Q" SNm="seq<12>_MC.Q"/><Net IoT="none" NNm="FB1_16_Q" SNm="new_reg<4>_MC.Q"/><Net IoT="none" NNm="FB1_4_Q" SNm="seq<13>_MC.Q"/><Net IoT="none" NNm="FB1_5_Q" SNm="seq<14>_MC.Q"/><Net IoT="none" NNm="FB1_6_Q" SNm="seq<15>_MC.Q"/><Net IoT="none" NNm="FB1_10_MC_CLK" SNm="FB1_10_MC_CLK"/><Net IoT="none" NNm="FB1_11_MC_CLK" SNm="FB1_11_MC_CLK"/><Net IoT="none" NNm="FB1_12_MC_CLK" SNm="FB1_12_MC_CLK"/><Net IoT="none" NNm="FB2_11_MC_CLK" SNm="FB2_11_MC_CLK"/><Net IoT="none" NNm="FB1_13_MC_CLK" SNm="FB1_13_MC_CLK"/><Net IoT="none" NNm="FB2_12_MC_CLK" SNm="FB2_12_MC_CLK"/><Net IoT="none" NNm="FB1_14_MC_CLK" SNm="FB1_14_MC_CLK"/><Net IoT="none" NNm="FB2_13_MC_CLK" SNm="FB2_13_MC_CLK"/><Net IoT="none" NNm="FB1_15_MC_CLK" SNm="FB1_15_MC_CLK"/><Net IoT="none" NNm="FB2_14_MC_CLK" SNm="FB2_14_MC_CLK"/><Net IoT="none" NNm="FB1_16_MC_CLK" SNm="FB1_16_MC_CLK"/><Net IoT="none" NNm="FB2_15_MC_CLK" SNm="FB2_15_MC_CLK"/><Net IoT="none" NNm="FB2_16_MC_CLK" SNm="FB2_16_MC_CLK"/><Net IoT="none" NNm="PT_GND" SNm="PT_GND"/><Net IoT="none" NNm="FB1_PT0" SNm="FB1_PT0"/><Net IoT="none" NNm="FB1_PT1" SNm="FB1_PT1"/><Net IoT="out" Loc="FB1_7" NNm="seq<1>" SNm="seq<1>"/><Net IoT="out" Loc="FB1_8" NNm="seq<2>" SNm="seq<2>"/><Net IoT="out" Loc="FB1_9" NNm="seq<3>" SNm="seq<3>"/><Net IoT="out" Loc="FB1_10" NNm="seq<4>" SNm="seq<4>"/><Net IoT="out" Loc="FB1_11" NNm="seq<5>" SNm="seq<5>"/><Net IoT="out" Loc="FB1_12" NNm="seq<6>" SNm="seq<6>"/><Net IoT="out" Loc="FB1_13" NNm="seq<7>" SNm="seq<7>"/><Net IoT="out" Loc="FB1_14" NNm="seq<8>" SNm="seq<8>"/><Net IoT="out" Loc="FB1_15" NNm="seq<9>" SNm="seq<9>"/><Globals><GlblBuf Nm="GCK0" GType="GCK"><IPort NNm="FB2_5_I"/></GlblBuf></Globals><Lb Nm="FB1"><LbT Nm="FB1_PT0" PtT="XBR_CT_X"><OPort NNm="FB1_PT0"/><IPort NNm="FB2_12_Q"/><IPort NNm="FB2_11_Q"/></LbT><LbT Nm="FB1_PT1" PtT="XBR_CT_X"><OPort NNm="FB1_PT1"/><IPort NNm="FB2_12_Q"/><IPort NNm="FB2_11_Q"/></LbT><LbT Nm="FB1_PT10" PtT="XBR_C"><OPort NNm="FB1_PT10"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT13" PtT="XBR_C"><OPort NNm="FB1_PT13"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT16" PtT="XBR_C"><OPort NNm="FB1_PT16"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT19" PtT="XBR_C"><OPort NNm="FB1_PT19"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT22" PtT="XBR_C"><OPort NNm="FB1_PT22"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT25" PtT="XBR_C"><OPort NNm="FB1_PT25"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT28" PtT="XBR_C"><OPort NNm="FB1_PT28"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT31" PtT="XBR_C"><OPort NNm="FB1_PT31"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT34" PtT="XBR_C"><OPort NNm="FB1_PT34"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT37" PtT="XBR_C"><OPort NNm="FB1_PT37"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT40" PtT="XBR_C"><OPort NNm="FB1_PT40"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT43" PtT="XBR_C"><OPort NNm="FB1_PT43"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT46" PtT="XBR_C"><OPort NNm="FB1_PT46"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT49" PtT="XBR_C"><OPort NNm="FB1_PT49"/><IPort NNm="FB2_12_Q"/></LbT><LbT Nm="FB1_PT52" PtT="XBR_C"><OPort NNm="FB1_PT52"/><IPort NNm="FB2_12_Q"/></LbT><Mc Nm="FB1_1"><ClkMux Nm="FB1_1_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_1_MC_CLK"/></ClkMux><XorMux Nm="FB1_1_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_1_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<10>"/></InBuf><OutBuf Nm="FB1_1_O" IOS="LVCMOS18"><IPort NNm="FB1_1_Q"/><OPort NNm="seq<10>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_1_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_1_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_1_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_2"><ClkMux Nm="FB1_2_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_2_MC_CLK"/></ClkMux><XorMux Nm="FB1_2_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_2_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<11>"/></InBuf><OutBuf Nm="FB1_2_O" IOS="LVCMOS18"><IPort NNm="FB1_2_Q"/><OPort NNm="seq<11>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_2_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_2_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_2_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_3"><ClkMux Nm="FB1_3_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_3_MC_CLK"/></ClkMux><XorMux Nm="FB1_3_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_3_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<12>"/></InBuf><OutBuf Nm="FB1_3_O" IOS="LVCMOS18"><IPort NNm="FB1_3_Q"/><OPort NNm="seq<12>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_3_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_3_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_3_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_4"><ClkMux Nm="FB1_4_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_4_MC_CLK"/></ClkMux><XorMux Nm="FB1_4_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_4_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<13>"/></InBuf><OutBuf Nm="FB1_4_O" IOS="LVCMOS18"><IPort NNm="FB1_4_Q"/><OPort NNm="seq<13>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_4_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_4_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_4_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_5"><ClkMux Nm="FB1_5_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_5_MC_CLK"/></ClkMux><XorMux Nm="FB1_5_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_5_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<14>"/></InBuf><OutBuf Nm="FB1_5_O" IOS="LVCMOS18"><IPort NNm="FB1_5_Q"/><OPort NNm="seq<14>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_5_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_5_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_5_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_6"><ClkMux Nm="FB1_6_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_6_MC_CLK"/></ClkMux><XorMux Nm="FB1_6_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_6_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<15>"/></InBuf><OutBuf Nm="FB1_6_O" IOS="LVCMOS18"><IPort NNm="FB1_6_Q"/><OPort NNm="seq<15>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_6_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_6_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_6_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_7"><ClkMux Nm="FB1_7_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_7_MC_CLK"/></ClkMux><XorMux Nm="FB1_7_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_7_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<1>"/></InBuf><OutBuf Nm="FB1_7_O" IOS="LVCMOS18"><IPort NNm="FB1_7_Q"/><OPort NNm="seq<1>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_7_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_7_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_7_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_8"><ClkMux Nm="FB1_8_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_8_MC_CLK"/></ClkMux><XorMux Nm="FB1_8_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_8_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<2>"/></InBuf><OutBuf Nm="FB1_8_O" IOS="LVCMOS18"><IPort NNm="FB1_8_Q"/><OPort NNm="seq<2>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_8_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_8_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_8_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_9"><ClkMux Nm="FB1_9_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_9_MC_CLK"/></ClkMux><XorMux Nm="FB1_9_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_9_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<3>"/></InBuf><OutBuf Nm="FB1_9_O" IOS="LVCMOS18"><IPort NNm="FB1_9_Q"/><OPort NNm="seq<3>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_9_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_9_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_9_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_10"><ClkMux Nm="FB1_10_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_10_MC_CLK"/></ClkMux><XorMux Nm="FB1_10_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_10_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<4>"/></InBuf><OutBuf Nm="FB1_10_O" IOS="LVCMOS18"><IPort NNm="FB1_10_Q"/><OPort NNm="seq<4>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_10_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_10_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_10_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_11"><ClkMux Nm="FB1_11_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_11_MC_CLK"/></ClkMux><XorMux Nm="FB1_11_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_11_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<5>"/></InBuf><OutBuf Nm="FB1_11_O" IOS="LVCMOS18"><IPort NNm="FB1_11_Q"/><OPort NNm="seq<5>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_11_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_11_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_12"><ClkMux Nm="FB1_12_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_12_MC_CLK"/></ClkMux><XorMux Nm="FB1_12_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_12_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<6>"/></InBuf><OutBuf Nm="FB1_12_O" IOS="LVCMOS18"><IPort NNm="FB1_12_Q"/><OPort NNm="seq<6>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_12_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_12_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_13"><ClkMux Nm="FB1_13_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_13_MC_CLK"/></ClkMux><XorMux Nm="FB1_13_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_13_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<7>"/></InBuf><OutBuf Nm="FB1_13_O" IOS="LVCMOS18"><IPort NNm="FB1_13_Q"/><OPort NNm="seq<7>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_13_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_13_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_13_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_14"><ClkMux Nm="FB1_14_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_14_MC_CLK"/></ClkMux><XorMux Nm="FB1_14_AND"><IPort NNm="FB1_PT10"/></XorMux><InBuf Nm="FB1_14_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<8>"/></InBuf><OutBuf Nm="FB1_14_O" IOS="LVCMOS18"><IPort NNm="FB1_14_Q"/><OPort NNm="seq<8>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_14_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_14_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_15"><ClkMux Nm="FB1_15_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_15_MC_CLK"/></ClkMux><XorMux Nm="FB1_15_AND"><IPort NNm="FB1_PT10"/></XorMux><FbMux Nm="FB1_15_N"><IPort NNm="FB1_15_Q"/></FbMux><InBuf Nm="FB1_15_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="seq<9>"/></InBuf><OutBuf Nm="FB1_15_O" IOS="LVCMOS18"><IPort NNm="FB1_15_Q"/><OPort NNm="seq<9>"/><CntlPort NNm="PT_VCC"/></OutBuf><DFlop Nm="FB1_15_FF"><FlopPort NNm="FB1_PT10" Port="D"/><FlopPort NNm="FB1_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_15_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB1_16"><ClkMux Nm="FB1_16_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB1_16_MC_CLK"/></ClkMux><FbMux Nm="FB1_16_N"><IPort NNm="FB1_16_Q"/></FbMux><DFlop Nm="FB1_16_FF"><FlopPort NNm="FB1_16_OR" Port="D"/><FlopPort NNm="FB1_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB1_16_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop><Or Nm="FB1_16_OR"><OPort NNm="FB1_16_OR"/><IPort NNm="FB1_PT1"/><IPort NNm="FB1_PT0"/></Or></Mc></Lb><Lb Nm="FB2"><LbT Nm="FB2_PT40" PtT="XBR_C"><OPort NNm="FB2_PT40"/><IPort NNm="FB2_16_Q"/></LbT><LbT Nm="FB2_PT43" PtT="XBR_C"><OPort NNm="FB2_PT43"/><IPort NNm="FB1_16_Q"/></LbT><LbT Nm="FB2_PT46" PtT="XBR_C"><OPort NNm="FB2_PT46"/><IPort NNm="FB1_15_Q"/></LbT><LbT Nm="FB2_PT49" PtT="XBR_C"><OPort NNm="FB2_PT49"/><IPort NNm="FB2_15_Q"/></LbT><LbT Nm="FB2_PT52" PtT="XBR_C"><OPort NNm="FB2_PT52"/><IPort NNm="FB2_13_Q"/></LbT><LbT Nm="FB2_PT55" PtT="XBR_C"><OPort NNm="FB2_PT55"/><IPort NNm="FB2_14_Q"/></LbT><Mc Nm="FB2_1"/><Mc Nm="FB2_2"/><Mc Nm="FB2_3"/><Mc Nm="FB2_4"/><Mc Nm="FB2_5"><InBuf Nm="FB2_5_I" IOS="LVCMOS18" DataGate="N"><IPort NNm="clk"/><OPort NNm="FB2_5_I"/></InBuf></Mc><Mc Nm="FB2_6"/><Mc Nm="FB2_7"/><Mc Nm="FB2_8"/><Mc Nm="FB2_9"/><Mc Nm="FB2_10"/><Mc Nm="FB2_11"><ClkMux Nm="FB2_11_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB2_11_MC_CLK"/></ClkMux><XorMux Nm="FB2_11_AND"><IPort NNm="FB2_PT40"/></XorMux><FbMux Nm="FB2_11_N"><IPort NNm="FB2_11_Q"/></FbMux><DFlop Nm="FB2_11_FF"><FlopPort NNm="FB2_PT40" Port="D"/><FlopPort NNm="FB2_11_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_11_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB2_12"><ClkMux Nm="FB2_12_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB2_12_MC_CLK"/></ClkMux><XorMux Nm="FB2_12_AND"><IPort NNm="FB2_PT43"/></XorMux><FbMux Nm="FB2_12_N"><IPort NNm="FB2_12_Q"/></FbMux><DFlop Nm="FB2_12_FF"><FlopPort NNm="FB2_PT43" Port="D"/><FlopPort NNm="FB2_12_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_12_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB2_13"><ClkMux Nm="FB2_13_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB2_13_MC_CLK"/></ClkMux><XorMux Nm="FB2_13_AND"><IPort NNm="FB2_PT46"/></XorMux><FbMux Nm="FB2_13_N"><IPort NNm="FB2_13_Q"/></FbMux><DFlop Nm="FB2_13_FF"><FlopPort NNm="FB2_PT46" Port="D"/><FlopPort NNm="FB2_13_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_13_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB2_14"><ClkMux Nm="FB2_14_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB2_14_MC_CLK"/></ClkMux><XorMux Nm="FB2_14_AND"><IPort NNm="FB2_PT49"/></XorMux><FbMux Nm="FB2_14_N"><IPort NNm="FB2_14_Q"/></FbMux><DFlop Nm="FB2_14_FF"><FlopPort NNm="FB2_PT49" Port="D"/><FlopPort NNm="FB2_14_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_14_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB2_15"><ClkMux Nm="FB2_15_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB2_15_MC_CLK"/></ClkMux><XorMux Nm="FB2_15_AND"><IPort NNm="FB2_PT52"/></XorMux><FbMux Nm="FB2_15_N"><IPort NNm="FB2_15_Q"/></FbMux><DFlop Nm="FB2_15_FF"><FlopPort NNm="FB2_PT52" Port="D"/><FlopPort NNm="FB2_15_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_15_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc><Mc Nm="FB2_16"><ClkMux Nm="FB2_16_MC_CLK" Rate="1"><IPort NNm="FB2_5_I"/><OPort NNm="FB2_16_MC_CLK"/></ClkMux><XorMux Nm="FB2_16_AND"><IPort NNm="FB2_PT55"/></XorMux><FbMux Nm="FB2_16_N"><IPort NNm="FB2_16_Q"/></FbMux><DFlop Nm="FB2_16_FF"><FlopPort NNm="FB2_PT55" Port="D"/><FlopPort NNm="FB2_16_MC_CLK" Port="CLK"/><FlopPort NNm="FB2_16_Q" Port="Q"/><FlopPort NNm="PT_GND" Port="RST"/><FlopPort NNm="PT_GND" Port="PST"/></DFlop></Mc></Lb></Document>
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