pn.mrp

用VHDL语言编写的PN码产生程序

Release 7.1.04i Map H.42
Xilinx Mapping Report File for Design 'pn'

Design Information
------------------
Command Line   : D:/Program Files/Xilinx ISE 7.1i/bin/nt/map.exe -ise
d:\nf\pn\pn.ise -intstyle ise -p xc4vfx12-sf363-12 -cm area -pr b -k 4 -c 100 -o
pn_map.ncd pn.ngd pn.pcf 
Target Device  : xc4vfx12
Target Package : sf363
Target Speed   : -12
Mapper Version : virtex4 -- $Revision: 1.26.6.4 $
Mapped Date    : Thu Apr 26 14:33:53 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:           8 out of  10,944    1%
  Number of 4 input LUTs:               1 out of  10,944    1%
Logic Distribution:
  Number of occupied Slices:                            5 out of   5,472    1%
    Number of Slices containing only related logic:       5 out of       5  100%
    Number of Slices containing unrelated logic:          0 out of       5    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:           1 out of  10,944    1%
  Number of bonded IOBs:                3 out of     240    1%
  Number of BUFG/BUFGCTRLs:             1 out of      32    3%
    Number used as BUFGs:                1
    Number used as BUFGCTRLs:            0

Total equivalent gate count for design:  70
Additional JTAG gate count for IOBs:  144
Peak Memory Usage:  173 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------

Section 5 - Removed Logic
-------------------------

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |             | Strength | Rate |              |          | Delay    |
+----------------------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| reset                              | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| seq                                | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW |              |          |          |
+----------------------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
--------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 3
Number of Equivalent Gates for Design = 70
Number of RPM Macros = 0
Number of Hard Macros = 0
PMV = 0
USR_ACCESS_VIRTEX4 = 0
BUFIO = 0
GT11CLK = 0
GT11 = 0
IDELAYCTRL = 0
FRAME_ECC_VIRTEX4 = 0
STARTUP_VIRTEX4 = 0
JTAGPPC = 0
ICAP_VIRTEX4 = 0
DPM = 0
DCI_TEST = 0
DCIRESET = 0
CAPTURE_VIRTEX4 = 0
BSCAN_VIRTEX4 = 0
OSERDES = 0
ISERDES = 0
BUFR = 0
EMAC = 0
PPC405_ADV = 0
MONITOR = 0
PMCD = 0
DCM_ADV = 0
DSP48 = 0
Unbonded IOBs = 0
Bonded IOBs = 3
XORs = 0
CARRY_INITs = 0
CARRY_SKIPs = 0
CARRY_MUXes = 0
Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MUXFs = 0
MULT_ANDs = 0
4 input LUTs used as Route-Thrus = 0
4 input LUTs = 1
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 7
Slice Flip Flops = 8
SliceMs = 0
SliceLs = 5
Slices = 5
F6 Muxes = 0
F5 Muxes = 0
F8 Muxes = 0
F7 Muxes = 0
Number of LUT signals with 4 loads = 0
Number of LUT signals with 3 loads = 0
Number of LUT signals with 2 loads = 0
Number of LUT signals with 1 load = 1
NGM Average fanout of LUT = 1.00
NGM Maximum fanout of LUT = 1
NGM Average fanin for LUT = 2.0000
Number of LUT symbols = 1