pn_test.vhd

用VHDL语言编写的PN码产生程序

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-- Company: 
-- Engineer:
--
-- Create Date:   14:22:23 04/26/2007
-- Design Name:   pn
-- Module Name:   pn_test.vhd
-- Project Name:  pn
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: pn
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY pn_test_vhd IS
END pn_test_vhd;

ARCHITECTURE behavior OF pn_test_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT pn
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;          
		seq : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';

	--Outputs
	SIGNAL seq :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: pn PORT MAP(
		reset => reset,
		clk => clk,
		seq => seq
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;
	 reset<='1' after 1ns;
	 clk<=not clk after 2ns;
END;