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(unused) 0 FB2_9 3 I/O
(unused) 0 FB2_10 5 I/O
registers_0 1 FB2_11 6 I/O (b)
registers<3> 1 FB2_12 8 I/O (b)
registers<2> 1 FB2_13 12 I/O (b)
registers<1> 1 FB2_14 13 I/O (b)
new_reg<2> 1 FB2_15 14 I/O (b)
new_reg<1> 1 FB2_16 16 I/O (b)
Signals Used by Logic in Function Block
1: new_reg<1> 3: new_reg<4> 5: registers<2>
2: new_reg<2> 4: registers<1> 6: seq<9>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
registers_0 X....................................... 1
registers<3> ..X..................................... 1
registers<2> .....X.................................. 1
registers<1> .X...................................... 1
new_reg<2> ....X................................... 1
new_reg<1> ...X.................................... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
FDCPE_new_reg1: FDCPE port map (new_reg(1),registers(1),clk,'0','0','1');
FDCPE_new_reg2: FDCPE port map (new_reg(2),registers(2),clk,'0','0','1');
FDCPE_new_reg4: FDCPE port map (new_reg(4),new_reg_D(4),clk,'0','0','1');
new_reg_D(4) <= ((registers(3) AND NOT registers_0)
OR (NOT registers(3) AND registers_0));
FDCPE_registers1: FDCPE port map (registers(1),new_reg(2),clk,'0','0','1');
FDCPE_registers2: FDCPE port map (registers(2),seq(9),clk,'0','0','1');
FDCPE_registers3: FDCPE port map (registers(3),new_reg(4),clk,'0','0','1');
FDCPE_registers_0: FDCPE port map (registers_0,new_reg(1),clk,'0','0','1');
FDCPE_seq1: FDCPE port map (seq(1),registers(3),clk,'0','0','1');
FDCPE_seq2: FDCPE port map (seq(2),registers(3),clk,'0','0','1');
FDCPE_seq3: FDCPE port map (seq(3),registers(3),clk,'0','0','1');
FDCPE_seq4: FDCPE port map (seq(4),registers(3),clk,'0','0','1');
FDCPE_seq5: FDCPE port map (seq(5),registers(3),clk,'0','0','1');
FDCPE_seq6: FDCPE port map (seq(6),registers(3),clk,'0','0','1');
FDCPE_seq7: FDCPE port map (seq(7),registers(3),clk,'0','0','1');
FDCPE_seq8: FDCPE port map (seq(8),registers(3),clk,'0','0','1');
FDCPE_seq9: FDCPE port map (seq(9),registers(3),clk,'0','0','1');
FDCPE_seq10: FDCPE port map (seq(10),registers(3),clk,'0','0','1');
FDCPE_seq11: FDCPE port map (seq(11),registers(3),clk,'0','0','1');
FDCPE_seq12: FDCPE port map (seq(12),registers(3),clk,'0','0','1');
FDCPE_seq13: FDCPE port map (seq(13),registers(3),clk,'0','0','1');
FDCPE_seq14: FDCPE port map (seq(14),registers(3),clk,'0','0','1');
FDCPE_seq15: FDCPE port map (seq(15),registers(3),clk,'0','0','1');
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FDDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
FTDCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XA2C32A-6-VQ44
--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XA2C32A-6-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 PGND 23 seq<6>
2 PGND 24 TDO
3 PGND 25 GND
4 GND 26 VCCIO-1.8
5 PGND 27 seq<5>
6 PGND 28 seq<4>
7 VCCIO-1.8 29 seq<3>
8 PGND 30 seq<2>
9 TDI 31 seq<1>
10 TMS 32 seq<15>
11 TCK 33 seq<14>
12 PGND 34 seq<13>
13 PGND 35 VCCAUX
14 PGND 36 seq<12>
15 VCC 37 seq<11>
16 PGND 38 seq<10>
17 GND 39 PGND
18 TIE 40 PGND
19 PGND 41 PGND
20 seq<9> 42 PGND
21 seq<8> 43 clk
22 seq<7> 44 PGND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
KPR = Unused I/O with weak keeper (leave unconnected)
WPU = Unused I/O with weak pull up (leave unconnected)
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
VCCAUX = Power supply for JTAG pins
VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I
VCCIO-1.8 = I/O supply voltage for LVCMOS18
VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I
VREF = Reference voltage for indicated input standard
*VREF = Reference voltage pin selected by software
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xa2c32a-6-VQ44
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Set Unused I/O Pin Termination : GROUND
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Enable Input Registers : ON
Function Block Fan-in Limit : 38
Use DATA_GATE Attribute : ON
Set Tristate Outputs to Termination Mode : FLOAT
Default Voltage Standard for All Outputs : LVCMOS18
Input Limit : 32
Pterm Limit : 36
</pre>
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