init.s

ads7843+5个串口+1个定时器+at91rm9200测试源程序

;//*********************************************************************************************************************
;//【  版          权  】Copyright (c) 2007-2008 http://gliethttp.cublog.cn
;//
;//【  文  件  版  本  】v1.x
;//
;//【  文  件  名  称  】init.s
;//
;//【  创  建  日  期  】2007-12-27
;//
;//【  功  能  描  述  】启动代码
;//*********************************************************************************************************************
 include AT91RM9200.inc
;//---------------------------------------------------------------------------------------------------------------------
;// IMPORT               OS_CPU_IRQ_ISR
;// IMPORT               OS_CPU_FIQ_ISR
;//---------------------------------------------------------------------------------------------------------------------
 CODE32
 AREA |Init|,CODE,READONLY
 ENTRY
resetvec        B           Reset_Handler
undefvec        B           .
swivec          B           .
pabtvec         B           .
dabtvec         B           .
rsvdvec         B           .
irqvec          ldr			pc, [pc,#-0xF20];//B           .;//OS_CPU_IRQ_ISR
fiqvec          ldr			pc, [pc,#-0xF20];//B           .;//OS_CPU_FIQ_ISR

Reset_Handler
	ldr		r0 ,=0x0
	ldr 	r1 ,=AT91C_AIC_IMR
	str 	r0 ,[r1]
	;////////////////////////
	;///////////////////////
	
	ldr		r1, = 0x00201000
	msr		cpsr_c, #(ARM_MODE_SVC | I_BIT | F_BIT)
	msr		spsr_cxsf, #(ARM_MODE_SVC | I_BIT | F_BIT)
	bic		r1, r1, #3
	mov		sp, r1
	
	IMPORT	AT91F_LowLevelInit
	bl		AT91F_LowLevelInit

	ldr		r0, =0x00000020
LoopWait
	subs	r0, r0, #1
	bhi		LoopWait


	ldr		r0, =AT91_Stack_Begin

	msr	CPSR_c, #(ARM_MODE_SVC | I_BIT | F_BIT)
	mov		r13, r0
	sub		r0, r0, #SVC_STACK_SIZE

	msr		CPSR_c, #(ARM_MODE_IRQ | I_BIT | F_BIT)
	mov		r13, r0
	sub		r0, r0, #IRQ_STACK_SIZE

	msr	CPSR_c, #(ARM_MODE_FIQ | I_BIT | F_BIT)
	mov		r13, r0
	sub		r0, r0, #FIQ_STACK_SIZE

	msr		CPSR_c, #(ARM_MODE_ABORT | I_BIT | F_BIT)
	mov		r13, r0
	sub		r0, r0, #ABT_STACK_SIZE

	msr		CPSR_c, #(ARM_MODE_UNDEF | I_BIT | F_BIT)
	mov		r13, r0 
	sub		r0, r0, #UND_STACK_SIZE

	msr		CPSR_c, #(ARM_MODE_SYS | I_BIT | F_BIT)
	mov		r13, r0
	sub		r0, r0, #SYS_STACK_SIZE

	msr		CPSR_c, #(ARM_MODE_SVC);//| I_BIT | F_BIT )

	  IMPORT   xCopy2SDRAM
	  mov	   r0,pc
	  mov	   r1,#0x20000000
	  cmps	   r0,r1
	  bge	   HOP
	  bl	   xCopy2SDRAM
	  ldr	   pc,=HOP
HOP
	add     r2, pc,#-(8+.-CInitData)  	; @ where to read values (relative)
	ldmia   r2, {r0, r1, r3, r4} 
	
	cmp         r0, r1                  ; Check that they are different
	beq         EndRW
LoopRW	
	cmp         r1, r3                  ; Copy init data
	ldrcc       r2, [r0], #4
	strcc       r2, [r1], #4
	bcc         LoopRW
EndRW

	mov         r2, #0
LoopZI	
	cmp         r3, r4                  ; Zero init
	strcc       r2, [r3], #4
	bcc         LoopZI
 
	b           EndInitC
                
CInitData
 	IMPORT      |Image$$RO$$Limit|      ; End of ROM code (=start of ROM data)
	IMPORT      |Image$$RW$$Base|       ; Base of RAM to initialise
	IMPORT      |Image$$ZI$$Base|       ; Base and limit of area
	IMPORT      |Image$$ZI$$Limit|      ; Top of zero init segment
	
	DCD     |Image$$RO$$Limit|      ; End of ROM code (=start of ROM data)
 	DCD     |Image$$RW$$Base|       ; Base of RAM to initialise
 	DCD     |Image$$ZI$$Base|       ; Base and limit of area
 	DCD     |Image$$ZI$$Limit|      ; Top of zero init segment
EndInitC
   	
Armboot_begin
;*********************************
;Jump to Main Routine
	  IMPORT   Main
      B        Main
here  B  	   .
;//---------------------------------------------------------------------------------------------------------------------
 END
;//⊙⊙⊙
;//⊙⊙⊙完了⊙⊙⊙
;//⊙⊙⊙over⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙⊙