📄 sfr26a.h
字号:
#pragma ADDRESS ad4_addr 03c8H /* A/D register 4 */
#pragma ADDRESS ad5_addr 03caH /* A/D register 5 */
#pragma ADDRESS ad6_addr 03ccH /* A/D register 6 */
#pragma ADDRESS ad7_addr 03ceH /* A/D register 7 */
#pragma ADDRESS adtrgcon_addr 03d2H /* A/D trigger control register */
#pragma ADDRESS adstat0_addr 03d3H /* A/D convert status register 0 */
#pragma ADDRESS adcon2_addr 03d4H /* A/D control register 2 */
#pragma ADDRESS adcon0_addr 03d6H /* A/D control register 0 */
#pragma ADDRESS adcon1_addr 03d7H /* A/D control register 1 */
#pragma ADDRESS p1_addr 03e1H /* Port P1 register */
#pragma ADDRESS pd1_addr 03e3H /* Port P1 direction register */
#pragma ADDRESS p6_addr 03ecH /* Port P6 register */
#pragma ADDRESS p7_addr 03edH /* Port P7 register */
#pragma ADDRESS pd6_addr 03eeH /* Port P6 direction register */
#pragma ADDRESS pd7_addr 03efH /* Port P7 direction register */
#pragma ADDRESS p8_addr 03f0H /* Port P8 register */
#pragma ADDRESS p9_addr 03f1H /* Port P9 register */
#pragma ADDRESS pd8_addr 03f2H /* Port P8 direction register */
#pragma ADDRESS pd9_addr 03f3H /* Port P9 direction register */
#pragma ADDRESS p10_addr 03f4H /* Port P10 register */
#pragma ADDRESS pd10_addr 03f6H /* Port P10 direction register */
#pragma ADDRESS pur0_addr 03fcH /* Pull-up control register 0 */
#pragma ADDRESS pur1_addr 03fdH /* Pull-up control register 1 */
#pragma ADDRESS pur2_addr 03feH /* Pull-up control register 2 */
#pragma ADDRESS pcr_addr 03ffH /* Port control register */
/********************************************************
* declare SFR bit *
********************************************************/
struct bit_def {
char b0:1;
char b1:1;
char b2:1;
char b3:1;
char b4:1;
char b5:1;
char b6:1;
char b7:1;
};
union byte_def{
struct bit_def bit;
char byte;
};
/*------------------------------------------------------
Processor mode register 0
------------------------------------------------------*/
union byte_def pm0_addr;
#define pm0 pm0_addr.byte
#define pm03 pm0_addr.bit.b3 /* Software reset bit */
/*------------------------------------------------------
Processor mode register 1
------------------------------------------------------*/
union byte_def pm1_addr;
#define pm1 pm1_addr.byte
#define pm10 pm1_addr.bit.b0 /* Flash data block access bit */
#define pm12 pm1_addr.bit.b2 /* Watchdog timer function select bit */
#define pm17 pm1_addr.bit.b7 /* Wait bit */
/*------------------------------------------------------
System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define cm0 cm0_addr.byte
#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */
#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */
#define cm02 cm0_addr.bit.b2 /* WAIT Mode peripheral function clock stop bit */
#define cm03 cm0_addr.bit.b3 /* Xcin-Xcout drive capacity select bit */
#define cm04 cm0_addr.bit.b4 /* Port Xc select bit */
#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */
#define cm06 cm0_addr.bit.b6 /* Main clock division select bit 0 */
#define cm07 cm0_addr.bit.b7 /* System clock select bit */
/*------------------------------------------------------
System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define cm1 cm1_addr.byte
#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */
#define cm11 cm1_addr.bit.b1 /* System clock select bit 1 */
#define cm15 cm1_addr.bit.b5 /* Xin-Xout drive capacity select bit */
#define cm16 cm1_addr.bit.b6 /* Main clock division select bit 1 */
#define cm17 cm1_addr.bit.b7 /* Main clock division select bit 1 */
/*------------------------------------------------------
Address match interrupt enable register
------------------------------------------------------*/
union byte_def aier_addr;
#define aier aier_addr.byte
#define aier0 aier_addr.bit.b0 /* Address match interrupt 0 enable bit */
#define aier1 aier_addr.bit.b1 /* Address match interrupt 1 enable bit */
/*------------------------------------------------------
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Enable write to CM0,CM1,CM2,ROCR,PLC0 and PCLKR registers */
#define prc1 prcr_addr.bit.b1 /* Enable write to PM0,PM1,PM2,TB2SC,INVC0 and INVC1 registers */
#define prc2 prcr_addr.bit.b2 /* Enable write to PD9 and PACR registers */
#define prc3 prcr_addr.bit.b3 /* Enable write to VCR2 and D4INT registers */
/*------------------------------------------------------
Oscillation stop detection register
------------------------------------------------------*/
union byte_def cm2_addr;
#define cm2 cm2_addr.byte
#define cm20 cm2_addr.bit.b0 /* Oscillation stop,reoscillation detection bit */
#define cm21 cm2_addr.bit.b1 /* System clock select bit 2 */
#define cm22 cm2_addr.bit.b2 /* Oscillation stop,reoscillation detection flag */
#define cm23 cm2_addr.bit.b3 /* Xin monitor flag */
#define cm27 cm2_addr.bit.b7 /* Operation select bit */
/*------------------------------------------------------
Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define wdts wdts_addr.byte
/*------------------------------------------------------
Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define wdc wdc_addr.byte
#define wdc5 wdc_addr.bit.b5 /* Cold start/warm start discrimination flag */
#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */
/*------------------------------------------------------
Voltage detection register 1
------------------------------------------------------*/
union byte_def vcr1_addr;
#define vcr1 vcr1_addr.byte
#define vcr13 vcr1_addr.bit.b3 /* Voltage down monitor flag */
/*------------------------------------------------------
Voltage detection register 2
------------------------------------------------------*/
union byte_def vcr2_addr;
#define vcr2 vcr2_addr.byte
#define vcr25 vcr2_addr.bit.b5 /* RAM retention limit detection monitor bit */
#define vcr26 vcr2_addr.bit.b6 /* Reset level monitor bit */
#define vcr27 vcr2_addr.bit.b7 /* Voltage down monitor bit */
/*------------------------------------------------------
PLL control register 0
------------------------------------------------------*/
union byte_def plc0_addr;
#define plc0 plc0_addr.byte
#define plc00 plc0_addr.bit.b0 /* PLL multiplying factor select bit */
#define plc01 plc0_addr.bit.b1 /* PLL multiplying factor select bit */
#define plc02 plc0_addr.bit.b2 /* PLL multiplying factor select bit */
#define plc07 plc0_addr.bit.b7 /* operation enable bit */
/*------------------------------------------------------
Processor mode register 2
------------------------------------------------------*/
union byte_def pm2_addr;
#define pm2 pm2_addr.byte
#define pm20 pm2_addr.bit.b0 /* Specifying wait when accessing SFR */
#define pm21 pm2_addr.bit.b1 /* System clock protective bit */
#define pm22 pm2_addr.bit.b2 /* WDT count source protective bit */
#define pm24 pm2_addr.bit.b4 /* P85/NMI configuration bit */
/*------------------------------------------------------
CRC input register
------------------------------------------------------*/
union byte_def crcin_addr;
#define crcin crcin_addr.byte
/*------------------------------------------------------
Voltage down detection interrupt register
------------------------------------------------------*/
union byte_def d4int_addr;
#define d4int d4int_addr.byte
#define d40 d4int_addr.bit.b0 /* Voltage down detection interrupt enable bit */
#define d41 d4int_addr.bit.b1 /* STOP mode deactivation control bit */
#define d42 d4int_addr.bit.b2 /* Voltage change detection flag */
#define d43 d4int_addr.bit.b3 /* WDT overflow detect flag */
#define df0 d4int_addr.bit.b4 /* Sampling clock select bit */
#define df1 d4int_addr.bit.b5 /* Sampling clock select bit */
/*------------------------------------------------------
Three-phase protect control register
------------------------------------------------------*/
union byte_def tprc_addr;
#define tprc tprc_addr.byte
#define tprc0 tprc_addr.bit.b0
/*------------------------------------------------------
On-chip oscillator control register
------------------------------------------------------*/
union byte_def rocr_addr;
#define rocr rocr_addr.byte
#define rocr0 rocr_addr.bit.b0 /* Frequency select bit */
#define rocr1 rocr_addr.bit.b1 /* */
#define rocr2 rocr_addr.bit.b2 /* Divider select bit */
#define rocr3 rocr_addr.bit.b3 /* */
/*------------------------------------------------------
Pin assignment control register
------------------------------------------------------*/
union byte_def pacr_addr;
#define pacr pacr_addr.byte
#define pacr0 pacr_addr.bit.b0 /* Pin enabling bit */
#define pacr1 pacr_addr.bit.b1 /* Pin enabling bit */
#define pacr2 pacr_addr.bit.b2 /* Pin enabling bit */
#define u1map pacr_addr.bit.b7 /* UART1 pin remapping bit */
/*------------------------------------------------------
Peripheral clock select register
------------------------------------------------------*/
union byte_def pclkr_addr;
#define pclkr pclkr_addr.byte
#define pclk0 pclkr_addr.bit.b0 /* Timers A,B clock select bit */
#define pclk1 pclkr_addr.bit.b1 /* SI/O clock select bit */
#define pclk5 pclkr_addr.bit.b5 /* Clock output function expansion select bit */
/*------------------------------------------------------
NMI digital debounce register
------------------------------------------------------*/
union byte_def nddr_addr;
#define nddr nddr_addr.byte
/*------------------------------------------------------
P17 digital debounce register
------------------------------------------------------*/
union byte_def p17ddr_addr;
#define p17ddr p17ddr_addr.byte
/*------------------------------------------------------
Three-phase PWM control register 0
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -