📄 sfr28.h
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#define fsc1_g1fs g1fs_addr.bit.b1 /* Channel 1 time measurement/waveform generation function select bit */
#define fsc2_g1fs g1fs_addr.bit.b2 /* Channel 2 time measurement/waveform generation function select bit */
#define fsc3_g1fs g1fs_addr.bit.b3 /* Channel 3 time measurement/waveform generation function select bit */
#define fsc4_g1fs g1fs_addr.bit.b4 /* Channel 4 time measurement/waveform generation function select bit */
#define fsc5_g1fs g1fs_addr.bit.b5 /* Channel 5 time measurement/waveform generation function select bit */
#define fsc6_g1fs g1fs_addr.bit.b6 /* Channel 6 time measurement/waveform generation function select bit */
#define fsc7_g1fs g1fs_addr.bit.b7 /* Channel 7 time measurement/waveform generation function select bit */
/*------------------------------------------------------
Divider register
------------------------------------------------------*/
union byte_def g1dv_addr;
#define g1dv g1dv_addr.byte
/*------------------------------------------------------
Interruput request register
------------------------------------------------------*/
union byte_def g1ir_addr;
#define g1ir g1ir_addr.byte
#define g1ir0 g1ir_addr.bit.b0 /* Interrupt request Ch 0 */
#define g1ir1 g1ir_addr.bit.b1 /* Interrupt request Ch 1 */
#define g1ir2 g1ir_addr.bit.b2 /* Interrupt request Ch 2 */
#define g1ir3 g1ir_addr.bit.b3 /* Interrupt request Ch 3 */
#define g1ir4 g1ir_addr.bit.b4 /* Interrupt request Ch 4 */
#define g1ir5 g1ir_addr.bit.b5 /* Interrupt request Ch 5 */
#define g1ir6 g1ir_addr.bit.b6 /* Interrupt request Ch 6 */
#define g1ir7 g1ir_addr.bit.b7 /* Interrupt request Ch 7 */
/*------------------------------------------------------
Interruput enable register 0
------------------------------------------------------*/
union byte_def g1ie0_addr;
#define g1ie0 g1ie0_addr.byte
#define g1ie00 g1ie0_addr.bit.b0 /* Interrupt enable 0 Ch 0 */
#define g1ie01 g1ie0_addr.bit.b1 /* Interrupt enable 0 Ch 1 */
#define g1ie02 g1ie0_addr.bit.b2 /* Interrupt enable 0 Ch 2 */
#define g1ie03 g1ie0_addr.bit.b3 /* Interrupt enable 0 Ch 3 */
#define g1ie04 g1ie0_addr.bit.b4 /* Interrupt enable 0 Ch 4 */
#define g1ie05 g1ie0_addr.bit.b5 /* Interrupt enable 0 Ch 5 */
#define g1ie06 g1ie0_addr.bit.b6 /* Interrupt enable 0 Ch 6 */
#define g1ie07 g1ie0_addr.bit.b7 /* Interrupt enable 0 Ch 7 */
/*------------------------------------------------------
Interruput enable register 1
------------------------------------------------------*/
union byte_def g1ie1_addr;
#define g1ie1 g1ie1_addr.byte
#define g1ie10 g1ie1_addr.bit.b0 /* Interrupt enable 1 Ch 0 */
#define g1ie11 g1ie1_addr.bit.b1 /* Interrupt enable 1 Ch 1 */
#define g1ie12 g1ie1_addr.bit.b2 /* Interrupt enable 1 Ch 2 */
#define g1ie13 g1ie1_addr.bit.b3 /* Interrupt enable 1 Ch 3 */
#define g1ie14 g1ie1_addr.bit.b4 /* Interrupt enable 1 Ch 4 */
#define g1ie15 g1ie1_addr.bit.b5 /* Interrupt enable 1 Ch 5 */
#define g1ie16 g1ie1_addr.bit.b6 /* Interrupt enable 1 Ch 6 */
#define g1ie17 g1ie1_addr.bit.b7 /* Interrupt enable 1 Ch 7 */
/*------------------------------------------------------
NMI digital debounce register
------------------------------------------------------*/
union byte_def nddr_addr;
#define nddr nddr_addr.byte
/*------------------------------------------------------
P17 digital debounce register
------------------------------------------------------*/
union byte_def p17ddr_addr;
#define p17ddr p17ddr_addr.byte
/*------------------------------------------------------
Three-phase PWM control regester 0
------------------------------------------------------*/
union byte_def invc0_addr;
#define invc0 invc0_addr.byte
#define inv00 invc0_addr.bit.b0 /* Effective interrupt output polarity select bit */
#define inv01 invc0_addr.bit.b1 /* Effective interrupt output specification bit */
#define inv02 invc0_addr.bit.b2 /* Mode select bit */
#define inv03 invc0_addr.bit.b3 /* Output control bit */
#define inv04 invc0_addr.bit.b4 /* Positive and negative phases concurrent output disable bit */
#define inv05 invc0_addr.bit.b5 /* Positive and negative phases concurrent output detect flag */
#define inv06 invc0_addr.bit.b6 /* Modulation mode select bit */
#define inv07 invc0_addr.bit.b7 /* Software trigger select bit */
/*------------------------------------------------------
Three-phase PWM control regester 1
------------------------------------------------------*/
union byte_def invc1_addr;
#define invc1 invc1_addr.byte
#define inv10 invc1_addr.bit.b0 /* Timer A1,A2,A4 start trigger signal select bit */
#define inv11 invc1_addr.bit.b1 /* Timer A1-1,A2-1,A4-1 control bit */
#define inv12 invc1_addr.bit.b2 /* Dead time timer count source select bit */
#define inv13 invc1_addr.bit.b3 /* Carrier wave detect flag */
#define inv14 invc1_addr.bit.b4 /* Output polarity control bit */
#define inv15 invc1_addr.bit.b5 /* Dead time invalid bit */
#define inv16 invc1_addr.bit.b6 /* Dead time timer trigger select bit */
/*------------------------------------------------------
Three-phase output buffer register 0
------------------------------------------------------*/
union byte_def idb0_addr;
#define idb0 idb0_addr.byte
#define du0 idb0_addr.bit.b0 /* U phase output buffer 0 */
#define dub0 idb0_addr.bit.b1 /* U~ phase output buffer 0 */
#define dv0 idb0_addr.bit.b2 /* V phase output buffer 0 */
#define dvb0 idb0_addr.bit.b3 /* V~ phase output buffer 0 */
#define dw0 idb0_addr.bit.b4 /* W phase output buffer 0 */
#define dwb0 idb0_addr.bit.b5 /* W~ phase output buffer 0 */
/*------------------------------------------------------
Three-phase output buffer register 1
------------------------------------------------------*/
union byte_def idb1_addr;
#define idb1 idb1_addr.byte
#define du1 idb1_addr.bit.b0 /* U phase output buffer 1 */
#define dub1 idb1_addr.bit.b1 /* U~ phase output buffer 1 */
#define dv1 idb1_addr.bit.b2 /* V phase output buffer 1 */
#define dvb1 idb1_addr.bit.b3 /* V~ phase output buffer 1 */
#define dw1 idb1_addr.bit.b4 /* W phase output buffer 1 */
#define dwb1 idb1_addr.bit.b5 /* W~ phase output buffer 1 */
/*------------------------------------------------------
Dead time timer ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def dtt_addr;
#define dtt dtt_addr.byte
/*------------------------------------------------------------------
Timer B2 interrupt occurrences frequency set counter ; Use "MOV" instruction when writing to this register.
-------------------------------------------------------------------*/
union byte_def ictb2_addr;
#define ictb2 ictb2_addr.byte
/*------------------------------------------------------
Position-data-retain function register
------------------------------------------------------*/
union byte_def pdrf_addr;
#define pdrf pdrf_addr.byte
#define pdrw pdrf_addr.bit.b0 /* W-phase position data retain bit */
#define pdrv pdrf_addr.bit.b1 /* V-phase position data retain bit */
#define pdru pdrf_addr.bit.b2 /* U-phase position data retain bit */
#define pdrt pdrf_addr.bit.b3 /* Retain-trigger polarity select bit */
/*------------------------------------------------------
ifsr2a
------------------------------------------------------*/
union byte_def ifsr2a_addr;
#define ifsr2a ifsr2a_addr.byte
#define ifsr20 ifsr2a_addr.bit.b0 /* Reserved bit */
#define ifsr26 ifsr2a_addr.bit.b6 /* Interrupt request cause select bit */
#define ifsr27 ifsr2a_addr.bit.b7 /* Interrupt request cause select bit */
/*------------------------------------------------------
ifsr
------------------------------------------------------*/
union byte_def ifsr_addr;
#define ifsr ifsr_addr.byte
#define ifsr0 ifsr_addr.bit.b0 /* INT0~ interrupt polarity switching bit */
#define ifsr1 ifsr_addr.bit.b1 /* INT1~ interrupt polarity switching bit */
#define ifsr2 ifsr_addr.bit.b2 /* INT2~ interrupt polarity switching bit */
#define ifsr3 ifsr_addr.bit.b3 /* INT3~ interrupt polarity switching bit */
#define ifsr4 ifsr_addr.bit.b4 /* INT4~ interrupt polarity switching bit */
#define ifsr5 ifsr_addr.bit.b5 /* INT5~ interrupt polarity switching bit */
#define ifsr6 ifsr_addr.bit.b6 /* Interrupt request cause select bit */
#define ifsr7 ifsr_addr.bit.b7 /* Interrupt request cause select bit */
/*------------------------------------------------------
SI/O3 transmit/receive registers
------------------------------------------------------*/
union byte_def s3trr_addr;
#define s3trr s3trr_addr.byte
/*------------------------------------------------------
SI/O3 bit rate generator ; Use "MOV" instruction when writing to these registers.
------------------------------------------------------*/
union byte_def s3brg_addr;
#define s3brg s3brg_addr.byte
/*------------------------------------------------------
SI/O4 transmit/receive registers
------------------------------------------------------*/
union byte_def s4trr_addr;
#define s4trr s4trr_addr.byte
/*------------------------------------------------------
SI/O4 bit rate generator ; Use "MOV" instruction when writing to these registers.
------------------------------------------------------*/
union byte_def s4brg_addr;
#define s4brg s4brg_addr.byte
/*------------------------------------------------------
UART2 special mode register 4
------------------------------------------------------*/
union byte_def u2smr4_addr;
#define u2smr4 u2smr4_addr.byte
#define stareq_u2smr4 u2smr4_addr.bit.b0 /* Start condition generate bit */
#define rstareq_u2smr4 u2smr4_addr.bit.b1 /* Restart condition generate bit */
#define stpreq_u2smr4 u2smr4_addr.bit.b2 /* Stop condition generate bit */
#define stspsel_u2smr4 u2smr4_addr.bit.b3 /* SCL,SDA output select bit */
#define ackd_u2smr4 u2smr4_addr.bit.b4 /* ACK data bit */
#define ackc_u2smr4 u2smr4_addr.bit.b5 /* ACK data output enable bit */
#define sclhi_u2smr4 u2smr4_addr.bit.b6 /* SCL output stop enable bit */
#define swc9_u2smr4 u2smr4_addr.bit.b7 /* SCL wait bit 3 */
/*------------------------------------------------------
UART2 special mode register 3
------------------------------------------------------*/
union byte_def u2smr3_addr;
#define u2smr3 u2smr3_addr.byte
#define ckph_u2smr3 u2smr3_addr.bit.b1 /* Clock phase set bit */
#define nodc_u2smr3 u2smr3_addr.bit.b3 /* Clock output select bit */
#define dl0_u2smr3 u2smr3_addr.bit.b5 /* SDA digital delay setup bit */
#define dl1_u2smr3 u2smr3_addr.bit.b6 /* SDA digital delay setup bit */
#define dl2_u2smr3 u2smr3_addr.bit.b7 /* SDA digital delay setup bit */
/*------------------------------------------------------
UART2 special mode register 2
------------------------------------------------------*/
union byte_def u2smr2_addr;
#define u2smr2 u2smr2_addr.byte
#define iicm2_u2smr2 u2smr2_addr.bit.b0 /* IIC mode selection bit 2 */
#define csc_u2smr2 u2smr2_addr.bit.b1 /* Clock-synchronous bit */
#define swc_u2smr2 u2smr2_addr.bit.b2 /* SCL wait output bit */
#define als_u2smr2 u2smr2_addr.bit.b3 /* SDA output stop bit */
#define stac_u2smr2 u2smr2_addr.bit.b4 /* UART2 initialization bit */
#define swc2_u2smr2 u2smr2_addr.bit.b5 /* SCL wait output bit 2 */
#define sdhi_u2smr2 u2smr2_addr.bit.b6 /* SDA output disable bit */
/*------------------------------------------------------
UART2 special mode register
------------------------------------------------------*/
union byte_def u2smr_addr;
#define u2smr u2smr_addr.byte
#define iicm_u2smr u2smr_addr.bit.b0 /* IIC mode selection bit */
#define abc_u2smr u2smr_addr.bit.b1 /* Arbitration lost detecting flag control bit */
#define bbs_u2smr u2smr_addr.bit.b2 /* Bus busy flag */
#define abscs_u2smr u2smr_addr.bit.b4 /* Bus collision detect sampling clock select bit */
#define acse_u2smr u2smr_addr.bit.b5 /* Auto clear function select bit of transmit enable bit */
#define sss_u2smr u2smr_addr.bit.b6 /* Transmit start condition select bit */
/*------------------------------------------------------
UART2 baud rate generation register ; Use "MOV" instruction when writing to these registers.
------------------------------------------------------*/
union byte_def u2brg_addr;
#define u2brg u2brg_addr.byte
/*------------------------------------------------------
UART2 transmit/receive control register 1
------------------------------------------------------*/
union byte_def u2c1_addr;
#define u2c1 u2c1_addr.byte
#define te_u2c1 u2c1_addr.bit.b0 /* Transmit enable bit */
#define ti_u2c1 u2c1_addr.bit.b1 /* Transmit buffer empty flag */
#define re_u2c1 u2c1_addr.bit.b2 /* Receive enable bit */
#define ri_u2c1 u2c1_addr.bit.b3 /* Receive complete flag */
#define u2irs u2c1_addr.bit.b4 /* UART2 transmit interrupt cause select bit */
#define u2rrm u2c1_addr.bit.b5 /* UART2 continuous receive mode enable bit */
#define u2lch u2c1_addr.bit.b6 /* Data logic select bit */
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