sfr28.h

基于瑞萨 M16C 的最新版本 IIC 通信

#define     cm20        cm2_addr.bit.b0     /* Oscillation stop,reoscillation detection bit */
#define     cm21        cm2_addr.bit.b1     /* System clock select bit 2 */
#define     cm22        cm2_addr.bit.b2     /* Oscillation stop,reoscillation detection flag */
#define     cm23        cm2_addr.bit.b3     /* Xin monitor flag */
#define     cm27        cm2_addr.bit.b7     /* Operation select bit */

/*------------------------------------------------------
    Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define     wdts        wdts_addr.byte

/*------------------------------------------------------
    Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define     wdc         wdc_addr.byte

#define     wdc5        wdc_addr.bit.b5     /* Cold start/warm start discrimination flag */
#define     wdc7        wdc_addr.bit.b7     /* Prescaler select bit */

/*------------------------------------------------------
	Voltage detection register 1
------------------------------------------------------*/
union byte_def vcr1_addr;
#define     vcr1        vcr1_addr.byte

#define     vcr13       vcr1_addr.bit.b3    /* Voltage down monitor flag */

/*------------------------------------------------------
	Voltage detection register 2
------------------------------------------------------*/
union byte_def vcr2_addr;
#define     vcr2        vcr2_addr.byte

#define     vcr25       vcr2_addr.bit.b5    /* RAM retention limit detection monitor bit */
#define     vcr26       vcr2_addr.bit.b6    /* Reset level monitor bit */
#define     vcr27       vcr2_addr.bit.b7    /* Voltage down monitor bit */

/*------------------------------------------------------
	PLL control register 0
------------------------------------------------------*/
union byte_def plc0_addr;
#define     plc0		plc0_addr.byte

#define     plc00       plc0_addr.bit.b0	/* PLL multiplying factor select bit */
#define     plc01       plc0_addr.bit.b1	/* PLL multiplying factor select bit */
#define     plc02       plc0_addr.bit.b2	/* PLL multiplying factor select bit */
#define     plc07       plc0_addr.bit.b7	/* operation enable bit */

/*------------------------------------------------------
    Processor mode register 2
------------------------------------------------------*/
union byte_def pm2_addr;
#define     pm2     pm2_addr.byte

#define     pm20        pm2_addr.bit.b0     /* Specifying wait when accessing SFR */
#define     pm21        pm2_addr.bit.b1     /* System clock protective bit */
#define     pm22        pm2_addr.bit.b2     /* WDT count source protective bit */
#define     pm24        pm2_addr.bit.b4     /* P85/NMI configuration bit */

/*------------------------------------------------------
    Voltage down detection interrupt register
------------------------------------------------------*/
union byte_def d4int_addr;
#define     d4int     d4int_addr.byte

#define     d40         d4int_addr.bit.b0   /* Voltage down detection interrupt enable bit */
#define     d41         d4int_addr.bit.b1   /* STOP mode deactivation control bit */
#define     d42         d4int_addr.bit.b2   /* Voltage change detection flag */
#define     d43         d4int_addr.bit.b3   /* WDT overflow detect flag */
#define     df0         d4int_addr.bit.b4   /* Sampling clock select bit */
#define     df1         d4int_addr.bit.b5   /* Sampling clock select bit */

/*------------------------------------------------------
    On-chip oscillator control register
------------------------------------------------------*/
union byte_def rocr_addr;
#define     rocr        rocr_addr.byte

#define     rocr0       rocr_addr.bit.b0    /* Frequency select bit */
#define     rocr1       rocr_addr.bit.b1    /*                      */
#define     rocr2       rocr_addr.bit.b2    /* Divider select bit */
#define     rocr3       rocr_addr.bit.b3    /*                    */

/*------------------------------------------------------
    Pin assignment control register
------------------------------------------------------*/
union byte_def pacr_addr;
#define     pacr        pacr_addr.byte

#define     pacr0       pacr_addr.bit.b0    /* Pin enabling bit */
#define     pacr1       pacr_addr.bit.b1    /* Pin enabling bit */
#define     pacr2       pacr_addr.bit.b2    /* Pin enabling bit */
#define     u1map       pacr_addr.bit.b7    /* UART1 pin remapping bit */

/*------------------------------------------------------
    Peripheral clock selec register
------------------------------------------------------*/
union byte_def pclkr_addr;
#define    pclkr        pclkr_addr.byte

#define    pclk0        pclkr_addr.bit.b0   /* Timers A,B clock select bit */
#define    pclk1        pclkr_addr.bit.b1   /* SI/O clock select bit */

/*------------------------------------------------------
    I2C data shift register
------------------------------------------------------*/
union byte_def s00_addr;
#define     s00         s00_addr.byte

/*------------------------------------------------------
    I2C address register
------------------------------------------------------*/
union byte_def s0d0_addr;
#define    s0d0         s0d0_addr.byte

#define    sad0         s0d0_addr.bit.b1
#define    sad1         s0d0_addr.bit.b2
#define    sad2         s0d0_addr.bit.b3
#define    sad3         s0d0_addr.bit.b4
#define    sad4         s0d0_addr.bit.b5
#define    sad5         s0d0_addr.bit.b6
#define    sad6         s0d0_addr.bit.b7

/*------------------------------------------------------
    I2C control register 0
------------------------------------------------------*/
union byte_def s1d0_addr;
#define    s1d0         s1d0_addr.byte

#define    bc0          s1d0_addr.bit.b0    /* Bit counter */
#define    bc1          s1d0_addr.bit.b1    /* Bit counter */
#define    bc2          s1d0_addr.bit.b2    /* Bit counter */
#define    es0          s1d0_addr.bit.b3    /* I2C-Bus interface enable bit */
#define    als          s1d0_addr.bit.b4    /* Data format selection bit */
#define    ihr          s1d0_addr.bit.b6    /* I2C-Bus interface reset bit */
#define    tiss         s1d0_addr.bit.b7    /* I2C-Bus interface pin input level selection bit */

/*------------------------------------------------------
    I2C clock control register
------------------------------------------------------*/
union byte_def s20_addr;
#define    s20          s20_addr.byte

#define    ccr0         s20_addr.bit.b0     /* SCL frequency control bits */
#define    ccr1         s20_addr.bit.b1     /* SCL frequency control bits */
#define    ccr2         s20_addr.bit.b2     /* SCL frequency control bits */
#define    ccr3         s20_addr.bit.b3     /* SCL frequency control bits */
#define    ccr4         s20_addr.bit.b4     /* SCL frequency control bits */
#define    fastmode     s20_addr.bit.b5     /* SCL mode specification bit */
#define    ackbit       s20_addr.bit.b6     /* ACK bit */
#define    ack          s20_addr.bit.b7     /* ACK clock bit */

/*------------------------------------------------------
    I2C start/stop condition control register
------------------------------------------------------*/
union byte_def s2d0_addr;
#define    s2d0         s2d0_addr.byte

#define    ssc0         s2d0_addr.bit.b0    /* START/STOP condition setting bits */
#define    ssc1         s2d0_addr.bit.b1    /* START/STOP condition setting bits */
#define    ssc2         s2d0_addr.bit.b2    /* START/STOP condition setting bits */
#define    ssc3         s2d0_addr.bit.b3    /* START/STOP condition setting bits */
#define    ssc4         s2d0_addr.bit.b4    /* START/STOP condition setting bits */
#define    sip          s2d0_addr.bit.b5    /* SCL/SDA interrupt pin polarity selection bit */
#define    sis          s2d0_addr.bit.b6    /* SCL/SDA interrupt pin selection bit */
#define    stspsel      s2d0_addr.bit.b7    /* START/STOP condition generation selection bit */

/*------------------------------------------------------
    I2C control register 1
------------------------------------------------------*/
union byte_def s3d0_addr;
#define    s3d0         s3d0_addr.byte

#define    sim          s3d0_addr.bit.b0    /* The interrupt enable bit for STOP condition detection */
#define    wit          s3d0_addr.bit.b1    /* The interrupt enable bit for data receive completion */
#define    ped          s3d0_addr.bit.b2    /* SDA/Port function switching bit */
#define    pec          s3d0_addr.bit.b3    /* SCL/Port function switching bit */
#define    sdam         s3d0_addr.bit.b4    /* The logic value monitor bit of SDA output */
#define    sclm         s3d0_addr.bit.b5    /* The logic value monitor bit of SCL output */
#define    ick0         s3d0_addr.bit.b6    /* I2C system clock selection bits */
#define    ick1         s3d0_addr.bit.b7    /* I2C system clock selection bits */

/*------------------------------------------------------
    I2C control register 2
------------------------------------------------------*/
union byte_def s4d0_addr;
#define    s4d0         s4d0_addr.byte

#define    toe			s4d0_addr.bit.b0    /* Timeout detection function enable bit */
#define    tof			s4d0_addr.bit.b1    /* Timeout detection flag */
#define    tosel		s4d0_addr.bit.b2    /* Timeout detection time selection bit */
#define    ick2			s4d0_addr.bit.b3    /* I2C system clock selection bits */
#define    ick3			s4d0_addr.bit.b4    /* I2C system clock selection bits */
#define    ick4			s4d0_addr.bit.b5    /* I2C system clock selection bits */
#define    scpin		s4d0_addr.bit.b7    /* STOP condition detection interrupt request bit */

/*------------------------------------------------------
    I2C status register
------------------------------------------------------*/
union byte_def s10_addr;
#define    s10          s10_addr.byte

#define    lrb          s10_addr.bit.b0     /* Last receive bit */
#define    adr0         s10_addr.bit.b1     /* General call detection flag */
#define    aas          s10_addr.bit.b2     /* Slave address comparison flag */
#define    al           s10_addr.bit.b3     /* Arbitration lost detection flag */
#define    pin          s10_addr.bit.b4     /* I2C-Bus interface interrupt request bit */
#define    bb           s10_addr.bit.b5     /* Bus busy flag */
#define    trx          s10_addr.bit.b6     /* Communication mode specifiation bits */
#define    mst          s10_addr.bit.b7     /* Communication mode specifiation bits */

/*------------------------------------------------------
    Base timer control register 0
------------------------------------------------------*/
union byte_def g1bcr0_addr;
#define     g1bcr0       g1bcr0_addr.byte

#define     bck0_g1bcr0     g1bcr0_addr.bit.b0 /* Count source select bit */
#define     bck1_g1bcr0     g1bcr0_addr.bit.b1 /* Count source select bit */
#define     rst4_g1bcr0     g1bcr0_addr.bit.b2 /* Base timer reset cause select bit */
#define     ch7insel_g1bcr0 g1bcr0_addr.bit.b6 /* Channel 7 input select bit */
#define     it_g1bcr0       g1bcr0_addr.bit.b7 /* Base timer overflow select bit */

/*------------------------------------------------------
    Base timer control register 1
------------------------------------------------------*/
union byte_def g1bcr1_addr;
#define     g1bcr1       g1bcr1_addr.byte

#define     rst1_g1bcr1  g1bcr1_addr.bit.b1  /* Base timer reset cause select bit 1 */
#define     rst2_g1bcr1  g1bcr1_addr.bit.b2  /* Base timer reset cause select bit 2 */
#define     bts_g1bcr1   g1bcr1_addr.bit.b4  /* Base timer start bit */
#define     ud0_g1bcr1   g1bcr1_addr.bit.b5  /* Counter increment/decrement control bit */
#define     ud1_g1bcr1   g1bcr1_addr.bit.b6  /* Counter increment/decrement control bit */

/*------------------------------------------------------
    Time measurement prescale register 6
------------------------------------------------------*/
union byte_def g1tpr6_addr;
#define     g1tpr6      g1tpr6_addr.byte

/*------------------------------------------------------
    Time measurement prescale register 7
------------------------------------------------------*/
union byte_def g1tpr7_addr;
#define     g1tpr7      g1tpr7_addr.byte

/*------------------------------------------------------
    Function enable register
------------------------------------------------------*/
union byte_def g1fe_addr;
#define     g1fe         g1fe_addr.byte

#define     ife0_g1fe    g1fe_addr.bit.b0   /* Channel 0 function enable bit */
#define     ife1_g1fe    g1fe_addr.bit.b1   /* Channel 1 function enable bit */
#define     ife2_g1fe    g1fe_addr.bit.b2   /* Channel 2 function enable bit */
#define     ife3_g1fe    g1fe_addr.bit.b3   /* Channel 3 function enable bit */
#define     ife4_g1fe    g1fe_addr.bit.b4   /* Channel 4 function enable bit */
#define     ife5_g1fe    g1fe_addr.bit.b5   /* Channel 5 function enable bit */
#define     ife6_g1fe    g1fe_addr.bit.b6   /* Channel 6 function enable bit */
#define     ife7_g1fe    g1fe_addr.bit.b7   /* Channel 7 function enable bit */

/*------------------------------------------------------
    Function select register
------------------------------------------------------*/
union byte_def g1fs_addr;
#define     g1fs         g1fs_addr.byte

#define     fsc0_g1fs    g1fs_addr.bit.b0   /* Channel 0 time measurement/waveform generation function select bit */