📄 sfr29.h
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/*------------------------------------------------------
ifsr2a
------------------------------------------------------*/
union byte_def ifsr2a_addr;
#define ifsr2a ifsr2a_addr.byte
#define ifsr20 ifsr2a_addr.bit.b0 /* Reserved bit */
#define ifsr21 ifsr2a_addr.bit.b1 /* Interrupt request cause select bit */
#define ifsr22 ifsr2a_addr.bit.b2 /* Interrupt request cause select bit */
#define ifsr26 ifsr2a_addr.bit.b6 /* Interrupt request cause select bit */
#define ifsr27 ifsr2a_addr.bit.b7 /* Interrupt request cause select bit */
/*------------------------------------------------------
ifsr
------------------------------------------------------*/
union byte_def ifsr_addr;
#define ifsr ifsr_addr.byte
#define ifsr0 ifsr_addr.bit.b0 /* INT0~ interrupt polarity switching bit */
#define ifsr1 ifsr_addr.bit.b1 /* INT1~ interrupt polarity switching bit */
#define ifsr2 ifsr_addr.bit.b2 /* INT2~ interrupt polarity switching bit */
#define ifsr3 ifsr_addr.bit.b3 /* INT3~ interrupt polarity switching bit */
#define ifsr4 ifsr_addr.bit.b4 /* INT4~ interrupt polarity switching bit */
#define ifsr5 ifsr_addr.bit.b5 /* INT5~ interrupt polarity switching bit */
#define ifsr6 ifsr_addr.bit.b6 /* Interrupt request cause select bit */
#define ifsr7 ifsr_addr.bit.b7 /* Interrupt request cause select bit */
/*------------------------------------------------------
SI/O3 transmit/receive registers
------------------------------------------------------*/
union byte_def s3trr_addr;
#define s3trr s3trr_addr.byte
/*------------------------------------------------------
SI/O3 bit rate generator ; Use "MOV" instruction when writing to these registers.
------------------------------------------------------*/
union byte_def s3brg_addr;
#define s3brg s3brg_addr.byte
/*------------------------------------------------------
SI/O4 transmit/receive registers
------------------------------------------------------*/
union byte_def s4trr_addr;
#define s4trr s4trr_addr.byte
/*------------------------------------------------------
SI/O4 bit rate generator ; Use "MOV" instruction when writing to these registers.
------------------------------------------------------*/
union byte_def s4brg_addr;
#define s4brg s4brg_addr.byte
/*------------------------------------------------------
UART2 special mode register 4
------------------------------------------------------*/
union byte_def u2smr4_addr;
#define u2smr4 u2smr4_addr.byte
#define stareq_u2smr4 u2smr4_addr.bit.b0 /* Start condition generate bit */
#define rstareq_u2smr4 u2smr4_addr.bit.b1 /* Restart condition generate bit */
#define stpreq_u2smr4 u2smr4_addr.bit.b2 /* Stop condition generate bit */
#define stspsel_u2smr4 u2smr4_addr.bit.b3 /* SCL,SDA output select bit */
#define ackd_u2smr4 u2smr4_addr.bit.b4 /* ACK data bit */
#define ackc_u2smr4 u2smr4_addr.bit.b5 /* ACK data output enable bit */
#define sclhi_u2smr4 u2smr4_addr.bit.b6 /* SCL output stop enable bit */
#define swc9_u2smr4 u2smr4_addr.bit.b7 /* SCL wait bit 3 */
/*------------------------------------------------------
UART2 special mode register 3
------------------------------------------------------*/
union byte_def u2smr3_addr;
#define u2smr3 u2smr3_addr.byte
#define ckph_u2smr3 u2smr3_addr.bit.b1 /* Clock phase set bit */
#define nodc_u2smr3 u2smr3_addr.bit.b3 /* Clock output select bit */
#define dl0_u2smr3 u2smr3_addr.bit.b5 /* SDA digital delay setup bit */
#define dl1_u2smr3 u2smr3_addr.bit.b6 /* SDA digital delay setup bit */
#define dl2_u2smr3 u2smr3_addr.bit.b7 /* SDA digital delay setup bit */
/*------------------------------------------------------
UART2 special mode register 2
------------------------------------------------------*/
union byte_def u2smr2_addr;
#define u2smr2 u2smr2_addr.byte
#define iicm2_u2smr2 u2smr2_addr.bit.b0 /* IIC mode selection bit 2 */
#define csc_u2smr2 u2smr2_addr.bit.b1 /* Clock-synchronous bit */
#define swc_u2smr2 u2smr2_addr.bit.b2 /* SCL wait output bit */
#define als_u2smr2 u2smr2_addr.bit.b3 /* SDA output stop bit */
#define stac_u2smr2 u2smr2_addr.bit.b4 /* UART2 initialization bit */
#define swc2_u2smr2 u2smr2_addr.bit.b5 /* SCL wait output bit 2 */
#define sdhi_u2smr2 u2smr2_addr.bit.b6 /* SDA output disable bit */
/*------------------------------------------------------
UART2 special mode register
------------------------------------------------------*/
union byte_def u2smr_addr;
#define u2smr u2smr_addr.byte
#define iicm_u2smr u2smr_addr.bit.b0 /* IIC mode selection bit */
#define abc_u2smr u2smr_addr.bit.b1 /* Arbitration lost detecting flag control bit */
#define bbs_u2smr u2smr_addr.bit.b2 /* Bus busy flag */
#define abscs_u2smr u2smr_addr.bit.b4 /* Bus collision detect sampling clock select bit */
#define acse_u2smr u2smr_addr.bit.b5 /* Auto clear function select bit of transmit enable bit */
#define sss_u2smr u2smr_addr.bit.b6 /* Transmit start condition select bit */
/*------------------------------------------------------
UART2 baud rate generation register ; Use "MOV" instruction when writing to these registers.
------------------------------------------------------*/
union byte_def u2brg_addr;
#define u2brg u2brg_addr.byte
/*------------------------------------------------------
UART2 transmit/receive control register 1
------------------------------------------------------*/
union byte_def u2c1_addr;
#define u2c1 u2c1_addr.byte
#define te_u2c1 u2c1_addr.bit.b0 /* Transmit enable bit */
#define ti_u2c1 u2c1_addr.bit.b1 /* Transmit buffer empty flag */
#define re_u2c1 u2c1_addr.bit.b2 /* Receive enable bit */
#define ri_u2c1 u2c1_addr.bit.b3 /* Receive complete flag */
#define u2irs u2c1_addr.bit.b4 /* UART2 transmit interrupt cause select bit */
#define u2rrm u2c1_addr.bit.b5 /* UART2 continuous receive mode enable bit */
#define u2lch u2c1_addr.bit.b6 /* Data logic select bit */
#define u2ere u2c1_addr.bit.b7 /* Error signal output enable bit */
/*------------------------------------------------------
Count start flag
------------------------------------------------------*/
union byte_def tabsr_addr;
#define tabsr tabsr_addr.byte
#define ta0s tabsr_addr.bit.b0 /* Timer A0 count start flag */
#define ta1s tabsr_addr.bit.b1 /* Timer A1 count start flag */
#define ta2s tabsr_addr.bit.b2 /* Timer A2 count start flag */
#define ta3s tabsr_addr.bit.b3 /* Timer A3 count start flag */
#define ta4s tabsr_addr.bit.b4 /* Timer A4 count start flag */
#define tb0s tabsr_addr.bit.b5 /* Timer B0 count start flag */
#define tb1s tabsr_addr.bit.b6 /* Timer B1 count start flag */
#define tb2s tabsr_addr.bit.b7 /* Timer B2 count start flag */
/*------------------------------------------------------
Clock prescaler reset flag
------------------------------------------------------*/
union byte_def cpsrf_addr;
#define cpsrf cpsrf_addr.byte
#define cpsr cpsrf_addr.bit.b7 /* Clock prescaler reset flag */
/*------------------------------------------------------
One-shot start flag
------------------------------------------------------*/
union byte_def onsf_addr;
#define onsf onsf_addr.byte
#define ta0os onsf_addr.bit.b0 /* Timer A0 one-shot start flag */
#define ta1os onsf_addr.bit.b1 /* Timer A1 one-shot start flag */
#define ta2os onsf_addr.bit.b2 /* Timer A2 one-shot start flag */
#define ta3os onsf_addr.bit.b3 /* Timer A3 one-shot start flag */
#define ta4os onsf_addr.bit.b4 /* Timer A4 one-shot start flag */
#define tazie onsf_addr.bit.b5 /* Z-phase input enable bit */
#define ta0tgl onsf_addr.bit.b6 /* Timer A0 event/trigger select bit */
#define ta0tgh onsf_addr.bit.b7 /* Timer A0 event/trigger select bit */
/*------------------------------------------------------
Trigger select register
------------------------------------------------------*/
union byte_def trgsr_addr;
#define trgsr trgsr_addr.byte
#define ta1tgl trgsr_addr.bit.b0 /* Timer A1 event/trigger select bit */
#define ta1tgh trgsr_addr.bit.b1 /* Timer A1 event/trigger select bit */
#define ta2tgl trgsr_addr.bit.b2 /* Timer A2 event/trigger select bit */
#define ta2tgh trgsr_addr.bit.b3 /* Timer A2 event/trigger select bit */
#define ta3tgl trgsr_addr.bit.b4 /* Timer A3 event/trigger select bit */
#define ta3tgh trgsr_addr.bit.b5 /* Timer A3 event/trigger select bit */
#define ta4tgl trgsr_addr.bit.b6 /* Timer A4 event/trigger select bit */
#define ta4tgh trgsr_addr.bit.b7 /* Timer A4 event/trigger select bit */
/*--------------------------------------------------------
Up/down flag ; Use "MOV" instruction to write to this register.
--------------------------------------------------------*/
union byte_def udf_addr; /* UP/down flag */
#define udf udf_addr.byte
/*------------------------------------------------------
Timer B2 special mode register
------------------------------------------------------*/
union byte_def tb2sc_addr;
#define tb2sc tb2sc_addr.byte
#define pwcon tb2sc_addr.bit.b0 /* Timer B2 reload timing switching bit */
#define ivpcr1 tb2sc_addr.bit.b1 /* Three phase output port ~SD control bit 1 */
#define tb0en tb2sc_addr.bit.b2 /* Timer B0 operation mode select bit */
#define tb1en tb2sc_addr.bit.b3 /* Timer B1 operation mode select bit */
#define tb2sel tb2sc_addr.bit.b4 /* Trigger select bit */
#define tb0trig tb2sc_addr.bit.b5 /* Timer B0 A/D Trigger select bit */
#define tb1trig tb2sc_addr.bit.b6 /* Timer B1 A/D Trigger select bit */
/*------------------------------------------------------
UART0 baud rate generation register ; Use "MOV" instruction when writing to these registers.
------------------------------------------------------*/
union byte_def u0brg_addr;
#define u0brg u0brg_addr.byte
/*------------------------------------------------------
UART1 baud rate generation register ; Use "MOV" instruction when writing to these registers.
------------------------------------------------------*/
union byte_def u1brg_addr;
#define u1brg u1brg_addr.byte
/*------------------------------------------------------
UART transmit/receive control register 2
------------------------------------------------------*/
union byte_def ucon_addr;
#define ucon ucon_addr.byte
#define u0irs ucon_addr.bit.b0 /* UART0 transmit interrupt cause select bit */
#define u1irs ucon_addr.bit.b1 /* UART1 transmit interrupt cause select bit */
#define u0rrm ucon_addr.bit.b2 /* UART0 continuous receive mode enable bit */
#define u1rrm ucon_addr.bit.b3 /* UART1 continuous receive mode enable bit */
#define clkmd0 ucon_addr.bit.b4 /* CLK/CLKS select bit 0 */
#define clkmd1 ucon_addr.bit.b5 /* CLK/CLKS select bit 1 */
#define rcsp ucon_addr.bit.b6 /* Separate RTS/CTS bit */
/*------------------------------------------------------
crc mode register
------------------------------------------------------*/
union byte_def crcmr_addr;
#define crcmr crcmr_addr.byte
#define crcps crcmr_addr.bit.b0
#define crcms crcmr_addr.bit.b7
/*------------------------------------------------------
AD trigger control register
------------------------------------------------------*/
union byte_def adtrgcon_addr;
#define adtrgcon adtrgcon_addr.byte
#define sse adtrgcon_addr.bit.b0 /* A/D operation mode select bit 2 */
#define dte adtrgcon_addr.bit.b1 /* A/D operation mode select bit 3 */
#define hptrg0 adtrgcon_addr.bit.b2 /* AN0 trigger select bit */
#define hptrg1 adtrgcon_addr.bit.b3 /* AN1 trigger select bit */
/*------------------------------------------------------
AD convert status register 0
------------------------------------------------------*/
union byte_def adstat0_addr;
#define adstat0 adstat0_addr.byte
#define aderr0 adstat0_addr.bit.b0 /* AN1 trigger status flag */
#define aderr1 adstat0_addr.bit.b1 /* Conversion termination flag */
#define adtcsf adstat0_addr.bit.b3 /* Delayed triggered sweep status flag */
#define adstt0 adstat0_addr.bit.b4 /* AN0 conversion status flag */
#define adstt1 adstat0_addr.bit.b5 /* AN1 conversion status flag */
#define adstrt0 adstat0_addr.bit.b6 /* AN0 conversion completion status flag */
#define adstrt1 adstat0_addr.bit.b7 /* AN1 conversion completion status flag */
/*------------------------------------------------------
A/D control register 2
------------------------------------------------------*/
union byte_def adcon2_addr;
#define adcon2 adcon2_addr.byte
#define smp adcon2_addr.bit.b0 /* A/D conversion method select bit */
#define adgsel0 adcon2_addr.bit.b1 /* AD input group select bit */
#define adgsel1 adcon2_addr.bit.b2 /* AD input group select bit */
#define cks2 adcon2_addr.bit.b4 /* Frequency select bit 2 */
#define trg1 adcon2_addr.bit.b5 /* Trigger select bit */
/*------------------------------------------------------
A/D control register 0
------------------------------------------------------*/
union byte_def adcon0_addr;
#define ad⌨️ 快捷键说明
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