sfr29.h

基于瑞萨 M16C 的最新版本 IIC 通信

------------------------------------------------------*/
union byte_def s2d0_addr;
#define    s2d0         s2d0_addr.byte

#define    ssc0         s2d0_addr.bit.b0    /* START/STOP condition setting bits */
#define    ssc1         s2d0_addr.bit.b1    /* START/STOP condition setting bits */
#define    ssc2         s2d0_addr.bit.b2    /* START/STOP condition setting bits */
#define    ssc3         s2d0_addr.bit.b3    /* START/STOP condition setting bits */
#define    ssc4         s2d0_addr.bit.b4    /* START/STOP condition setting bits */
#define    sip          s2d0_addr.bit.b5    /* SCL/SDA interrupt pin polarity selection bit */
#define    sis          s2d0_addr.bit.b6    /* SCL/SDA interrupt pin selection bit */
#define    stspsel      s2d0_addr.bit.b7    /* START/STOP condition generation selection bit */

/*------------------------------------------------------
    I2C control register 1
------------------------------------------------------*/
union byte_def s3d0_addr;
#define    s3d0         s3d0_addr.byte

#define    sim          s3d0_addr.bit.b0    /* The interrupt enable bit for STOP condition detection */
#define    wit          s3d0_addr.bit.b1    /* The interrupt enable bit for data receive completion */
#define    ped          s3d0_addr.bit.b2    /* SDA/Port function switching bit */
#define    pec          s3d0_addr.bit.b3    /* SCL/Port function switching bit */
#define    sdam         s3d0_addr.bit.b4    /* The logic value monitor bit of SDA output */
#define    sclm         s3d0_addr.bit.b5    /* The logic value monitor bit of SCL output */
#define    ick0         s3d0_addr.bit.b6    /* I2C system clock selection bits */
#define    ick1         s3d0_addr.bit.b7    /* I2C system clock selection bits */

/*------------------------------------------------------
    I2C control register 2
------------------------------------------------------*/
union byte_def s4d0_addr;
#define    s4d0         s4d0_addr.byte

#define    toe			s4d0_addr.bit.b0    /* Timeout detection function enable bit */
#define    tof			s4d0_addr.bit.b1    /* Timeout detection flag */
#define    tosel		s4d0_addr.bit.b2    /* Timeout detection time selection bit */
#define    ick2			s4d0_addr.bit.b3    /* I2C system clock selection bits */
#define    ick3			s4d0_addr.bit.b4    /* I2C system clock selection bits */
#define    ick4			s4d0_addr.bit.b5    /* I2C system clock selection bits */
#define    scpin		s4d0_addr.bit.b7    /* STOP condition detection interrupt request bit */

/*------------------------------------------------------
    I2C status register
------------------------------------------------------*/
union byte_def s10_addr;
#define    s10          s10_addr.byte

#define    lrb          s10_addr.bit.b0     /* Last receive bit */
#define    adr0         s10_addr.bit.b1     /* General call detection flag */
#define    aas          s10_addr.bit.b2     /* Slave address comparison flag */
#define    al           s10_addr.bit.b3     /* Arbitration lost detection flag */
#define    pin          s10_addr.bit.b4     /* I2C-Bus interface interrupt request bit */
#define    bb           s10_addr.bit.b5     /* Bus busy flag */
#define    trx          s10_addr.bit.b6     /* Communication mode specifiation bits */
#define    mst          s10_addr.bit.b7     /* Communication mode specifiation bits */

/*------------------------------------------------------
    Base timer control register 0
------------------------------------------------------*/
union byte_def g1bcr0_addr;
#define     g1bcr0       g1bcr0_addr.byte

#define     bck0_g1bcr0     g1bcr0_addr.bit.b0 /* Count source select bit */
#define     bck1_g1bcr0     g1bcr0_addr.bit.b1 /* Count source select bit */
#define     rst4_g1bcr0     g1bcr0_addr.bit.b2 /* Base timer reset cause select bit */
#define     ch7insel_g1bcr0 g1bcr0_addr.bit.b6 /* Channel 7 input select bit */
#define     it_g1bcr0       g1bcr0_addr.bit.b7 /* Base timer overflow select bit */

/*------------------------------------------------------
    Base timer control register 1
------------------------------------------------------*/
union byte_def g1bcr1_addr;
#define     g1bcr1       g1bcr1_addr.byte

#define     rst1_g1bcr1  g1bcr1_addr.bit.b1  /* Base timer reset cause select bit 1 */
#define     rst2_g1bcr1  g1bcr1_addr.bit.b2  /* Base timer reset cause select bit 2 */
#define     bts_g1bcr1   g1bcr1_addr.bit.b4  /* Base timer start bit */
#define     ud0_g1bcr1   g1bcr1_addr.bit.b5  /* Counter increment/decrement control bit */
#define     ud1_g1bcr1   g1bcr1_addr.bit.b6  /* Counter increment/decrement control bit */

/*------------------------------------------------------
    Time measurement prescale register 6
------------------------------------------------------*/
union byte_def g1tpr6_addr;
#define     g1tpr6      g1tpr6_addr.byte

/*------------------------------------------------------
    Time measurement prescale register 7
------------------------------------------------------*/
union byte_def g1tpr7_addr;
#define     g1tpr7      g1tpr7_addr.byte

/*------------------------------------------------------
    Function enable register
------------------------------------------------------*/
union byte_def g1fe_addr;
#define     g1fe         g1fe_addr.byte

#define     ife0_g1fe    g1fe_addr.bit.b0   /* Channel 0 function enable bit */
#define     ife1_g1fe    g1fe_addr.bit.b1   /* Channel 1 function enable bit */
#define     ife2_g1fe    g1fe_addr.bit.b2   /* Channel 2 function enable bit */
#define     ife3_g1fe    g1fe_addr.bit.b3   /* Channel 3 function enable bit */
#define     ife4_g1fe    g1fe_addr.bit.b4   /* Channel 4 function enable bit */
#define     ife5_g1fe    g1fe_addr.bit.b5   /* Channel 5 function enable bit */
#define     ife6_g1fe    g1fe_addr.bit.b6   /* Channel 6 function enable bit */
#define     ife7_g1fe    g1fe_addr.bit.b7   /* Channel 7 function enable bit */

/*------------------------------------------------------
    Function select register
------------------------------------------------------*/
union byte_def g1fs_addr;
#define     g1fs         g1fs_addr.byte

#define     fsc0_g1fs    g1fs_addr.bit.b0   /* Channel 0 time measurement/waveform generation function select bit */
#define     fsc1_g1fs    g1fs_addr.bit.b1   /* Channel 1 time measurement/waveform generation function select bit */
#define     fsc2_g1fs    g1fs_addr.bit.b2   /* Channel 2 time measurement/waveform generation function select bit */
#define     fsc3_g1fs    g1fs_addr.bit.b3   /* Channel 3 time measurement/waveform generation function select bit */
#define     fsc4_g1fs    g1fs_addr.bit.b4   /* Channel 4 time measurement/waveform generation function select bit */
#define     fsc5_g1fs    g1fs_addr.bit.b5   /* Channel 5 time measurement/waveform generation function select bit */
#define     fsc6_g1fs    g1fs_addr.bit.b6   /* Channel 6 time measurement/waveform generation function select bit */
#define     fsc7_g1fs    g1fs_addr.bit.b7   /* Channel 7 time measurement/waveform generation function select bit */

/*------------------------------------------------------
    Divider register
------------------------------------------------------*/
union byte_def g1dv_addr;
#define     g1dv        g1dv_addr.byte

/*------------------------------------------------------
    Interruput request register
------------------------------------------------------*/
union byte_def g1ir_addr;
#define     g1ir         g1ir_addr.byte

#define     g1ir0        g1ir_addr.bit.b0   /* Interrupt request Ch 0 */
#define     g1ir1        g1ir_addr.bit.b1   /* Interrupt request Ch 1 */
#define     g1ir2        g1ir_addr.bit.b2   /* Interrupt request Ch 2 */
#define     g1ir3        g1ir_addr.bit.b3   /* Interrupt request Ch 3 */
#define     g1ir4        g1ir_addr.bit.b4   /* Interrupt request Ch 4 */
#define     g1ir5        g1ir_addr.bit.b5   /* Interrupt request Ch 5 */
#define     g1ir6        g1ir_addr.bit.b6   /* Interrupt request Ch 6 */
#define     g1ir7        g1ir_addr.bit.b7   /* Interrupt request Ch 7 */

/*------------------------------------------------------
    Interruput enable register 0
------------------------------------------------------*/
union byte_def g1ie0_addr;
#define     g1ie0        g1ie0_addr.byte

#define     g1ie00       g1ie0_addr.bit.b0  /* Interrupt enable 0 Ch 0 */
#define     g1ie01       g1ie0_addr.bit.b1  /* Interrupt enable 0 Ch 1 */
#define     g1ie02       g1ie0_addr.bit.b2  /* Interrupt enable 0 Ch 2 */
#define     g1ie03       g1ie0_addr.bit.b3  /* Interrupt enable 0 Ch 3 */
#define     g1ie04       g1ie0_addr.bit.b4  /* Interrupt enable 0 Ch 4 */
#define     g1ie05       g1ie0_addr.bit.b5  /* Interrupt enable 0 Ch 5 */
#define     g1ie06       g1ie0_addr.bit.b6  /* Interrupt enable 0 Ch 6 */
#define     g1ie07       g1ie0_addr.bit.b7  /* Interrupt enable 0 Ch 7 */

/*------------------------------------------------------
    Interruput enable register 1
------------------------------------------------------*/
union byte_def g1ie1_addr;
#define     g1ie1        g1ie1_addr.byte

#define     g1ie10       g1ie1_addr.bit.b0  /* Interrupt enable 1 Ch 0 */
#define     g1ie11       g1ie1_addr.bit.b1  /* Interrupt enable 1 Ch 1 */
#define     g1ie12       g1ie1_addr.bit.b2  /* Interrupt enable 1 Ch 2 */
#define     g1ie13       g1ie1_addr.bit.b3  /* Interrupt enable 1 Ch 3 */
#define     g1ie14       g1ie1_addr.bit.b4  /* Interrupt enable 1 Ch 4 */
#define     g1ie15       g1ie1_addr.bit.b5  /* Interrupt enable 1 Ch 5 */
#define     g1ie16       g1ie1_addr.bit.b6  /* Interrupt enable 1 Ch 6 */
#define     g1ie17       g1ie1_addr.bit.b7  /* Interrupt enable 1 Ch 7 */

/*------------------------------------------------------
    NMI digital debounce register
------------------------------------------------------*/
union byte_def nddr_addr;
#define     nddr        nddr_addr.byte

/*------------------------------------------------------
    P17 digital debounce register
------------------------------------------------------*/
union byte_def p17ddr_addr;
#define     p17ddr      p17ddr_addr.byte

/*------------------------------------------------------
    Three-phase PWM control regester 0
------------------------------------------------------*/
union byte_def invc0_addr;
#define     invc0       invc0_addr.byte

#define     inv00       invc0_addr.bit.b0   /* Effective interrupt output polarity select bit */
#define     inv01       invc0_addr.bit.b1   /* Effective interrupt output specification bit */
#define     inv02       invc0_addr.bit.b2   /* Mode select bit */
#define     inv03       invc0_addr.bit.b3   /* Output control bit */
#define     inv04       invc0_addr.bit.b4   /* Positive and negative phases concurrent output disable bit */
#define     inv05       invc0_addr.bit.b5   /* Positive and negative phases concurrent output detect flag */
#define     inv06       invc0_addr.bit.b6   /* Modulation mode select bit */
#define     inv07       invc0_addr.bit.b7   /* Software trigger select bit */

/*------------------------------------------------------
    Three-phase PWM control regester 1
------------------------------------------------------*/
union byte_def invc1_addr;
#define     invc1       invc1_addr.byte

#define     inv10       invc1_addr.bit.b0   /* Timer A1,A2,A4 start trigger signal select bit */
#define     inv11       invc1_addr.bit.b1   /* Timer A1-1,A2-1,A4-1 control bit */
#define     inv12       invc1_addr.bit.b2   /* Dead time timer count source select bit */
#define     inv13       invc1_addr.bit.b3   /* Carrier wave detect flag */
#define     inv14       invc1_addr.bit.b4   /* Output polarity control bit */
#define     inv15       invc1_addr.bit.b5   /* Dead time invalid bit */
#define     inv16       invc1_addr.bit.b6   /* Dead time timer trigger select bit */

/*------------------------------------------------------
    Three-phase output buffer register 0
------------------------------------------------------*/
union byte_def idb0_addr;
#define     idb0        idb0_addr.byte

#define     du0         idb0_addr.bit.b0    /* U  phase output buffer 0 */
#define     dub0        idb0_addr.bit.b1    /* U~ phase output buffer 0 */
#define     dv0         idb0_addr.bit.b2    /* V  phase output buffer 0 */
#define     dvb0        idb0_addr.bit.b3    /* V~ phase output buffer 0 */
#define     dw0         idb0_addr.bit.b4    /* W  phase output buffer 0 */
#define     dwb0        idb0_addr.bit.b5    /* W~ phase output buffer 0 */

/*------------------------------------------------------
    Three-phase output buffer register 1
------------------------------------------------------*/
union byte_def idb1_addr;
#define     idb1        idb1_addr.byte

#define     du1         idb1_addr.bit.b0    /* U  phase output buffer 1 */
#define     dub1        idb1_addr.bit.b1    /* U~ phase output buffer 1 */
#define     dv1         idb1_addr.bit.b2    /* V  phase output buffer 1 */
#define     dvb1        idb1_addr.bit.b3    /* V~ phase output buffer 1 */
#define     dw1         idb1_addr.bit.b4    /* W  phase output buffer 1 */
#define     dwb1        idb1_addr.bit.b5    /* W~ phase output buffer 1 */

/*------------------------------------------------------
     Dead time timer ; Use "MOV" instruction when writing to this register.
------------------------------------------------------*/
union byte_def dtt_addr;
#define     dtt         dtt_addr.byte

/*------------------------------------------------------------------
     Timer B2 interrupt occurrences frequency set counter 
     ; Use "MOV" instruction when writing to this register.
-------------------------------------------------------------------*/
union byte_def ictb2_addr;
#define     ictb2       ictb2_addr.byte

/*------------------------------------------------------
    Position-data-retain function register
------------------------------------------------------*/
union byte_def pdrf_addr;
#define     pdrf        pdrf_addr.byte

#define     pdrw        pdrf_addr.bit.b0    /* W-phase position data retain bit */
#define     pdrv        pdrf_addr.bit.b1    /* V-phase position data retain bit */
#define     pdru        pdrf_addr.bit.b2    /* U-phase position data retain bit */
#define     pdrt        pdrf_addr.bit.b3    /* Retain-trigger polarity select bit */

/*------------------------------------------------------
    Port function control register
------------------------------------------------------*/
union byte_def pfcr_addr;
#define     pfcr        pfcr_addr.byte

#define     pfc0        pfcr_addr.bit.b0
#define     pfc1        pfcr_addr.bit.b1
#define     pfc2        pfcr_addr.bit.b2
#define     pfc3        pfcr_addr.bit.b3
#define     pfc4        pfcr_addr.bit.b4
#define     pfc5        pfcr_addr.bit.b5