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📄 iom16c62p.h

📁 基于瑞萨 M16C 的最新版本 IIC 通信
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/*------------------------------------------------------
    Flash memory control register 1 //0x01b5
------------------------------------------------------*/
union st_fmr1 {		           /*    Flash identification register         */
    struct{
     unsigned char         :1; /* Reserved bit   */
     unsigned char    FMR11:1; /* EW1 mode select bit */
     unsigned char         :1; /* Reserved bit   */
     unsigned char         :1; /* Reserved bit   */
     unsigned char         :1; /* Reserved bit	*/
     unsigned char         :1; /* Reserved bit    */
     unsigned char    FMR16:1; /* Lock bit status flag */
     unsigned char         :1; /* Reserved bit   */
    }BIT;
    unsigned char  BYTE;
};

/*------------------------------------------------------
    Flash memory control register 0 //0x01b7
------------------------------------------------------*/
union st_fmr0 {		           /*    Flash identification register         */
    struct{
     unsigned char    FMR00:1; /* RY/BY~ status flag */
     unsigned char    FMR01:1; /* EW0 mode select bit */
     unsigned char    FMR02:1; /* Lock bit disable bit */
     unsigned char    FMSTP:1; /* Flash memory stop bit */
     unsigned char         :1; /* Reserved bit	*/
     unsigned char    FMR05:1; /* User ROM area select bit */
     unsigned char    FMR06:1; /* Program status flag */
     unsigned char    FMR07:1; /* Erase status flag */
    }BIT;
    unsigned char  BYTE;
};

/*------------------------------------------------------
   Address match interrupt register 2 //0x01b8
-----------------------------------------------------*/
union st_rmad2 {
   struct{
	unsigned char RMAD2L;     /* Address match interrupt register 2 low  8 bit */
	unsigned char RMAD2M;     /* Address match interrupt register 2 mid  8 bit */
	unsigned char RMAD2H;     /* Address match interrupt register 2 high 8 bit */
	unsigned char NC;         /* non use 									   */
   } BYTE;					  /* Byte access								   */
   unsigned long   DWORD;	  /*	Word Access								   */
};							  /* Address match interrupt register 2 32 bit 	   */


/*------------------------------------------------------
    Address match interrupt enable register 2 //0x01bb
------------------------------------------------------*/
union st_aier2 {		           /* Address match interrupt enable register 2        */
    struct{
     unsigned char    AIER20:1; /* Address match interrupt 2 enable bit */
     unsigned char    AIER21:1; /* Address match interrupt 3 enable bit */
     unsigned char          :1; /* Nothing assigned */
     unsigned char          :1; /* Nothing assigned */
     unsigned char          :1; /* Nothing assigned	*/
     unsigned char          :1; /* Nothing assigned */
     unsigned char          :1; /* Nothing assigned */
     unsigned char          :1; /* Nothing assigned */
    }BIT;
    unsigned char  BYTE;
};

/*------------------------------------------------------
   Address match interrupt register 3 //0x01bc
-----------------------------------------------------*/
union st_rmad3 {
   struct{
	unsigned char RMAD3L;     /* Address match interrupt register 3 low  8 bit */
	unsigned char RMAD3M;     /* Address match interrupt register 3 mid  8 bit */
	unsigned char RMAD3H;     /* Address match interrupt register 3 high 8 bit */
	unsigned char NC;         /* non use 									   */
   } BYTE;					  /* Byte access								   */
   unsigned long   DWORD;	  /*	Word Access								   */
};							  /* Address match interrupt register 3 32 bit 	   */

/*------------------------------------------------------
    Peripheral clock select register //0x025e
------------------------------------------------------*/
union st_pclkr {		           /* Peripheral clock select register        */
    struct{
     unsigned char    PCLK0 :1; /* TimerA,B clock select bit */
     unsigned char    PCLK1 :1; /* SI/O clock select bit */
     unsigned char          :1; /* Reserved bit,set to 0 */
     unsigned char          :1; /* Reserved bit,set to 0 */
     unsigned char          :1; /* Reserved bit,set to 0	*/
     unsigned char          :1; /* Reserved bit,set to 0 */
     unsigned char          :1; /* Reserved bit,set to 0 */
     unsigned char          :1; /* Reserved bit,set to 0 */
    }BIT;
    unsigned char  BYTE;
};

/*------------------------------------------------------
    Timer B3,4,5 Count start flag //0x0340
------------------------------------------------------*/
union st_tbsr {              /* union tbsr    	   					*/
	struct {                 /* Bit  Access 		   				*/
	 unsigned char 		:1;  /* Nothing Assigned					*/
	 unsigned char 		:1;  /* Nothing Assigned					*/
	 unsigned char 		:1;  /* Nothing Assigned					*/
	 unsigned char 		:1;  /* Nothing Assigned					*/
	 unsigned char 		:1;  /* Nothing Assigned					*/
	 unsigned char 	TB3S:1;  /* Timer B3 count start flag 			*/
	 unsigned char 	TB4S:1;  /* Timer B4 count start flag 			*/
	 unsigned char 	TB5S:1;  /* Timer B5 count start flag 			*/
	} BIT;   		         /*        						    	*/
	unsigned  char BYTE;     /*  Byte Access 						*/
};                           /* Timer B3,4,5 Count start flag       */

/*------------------------------------------------------
   Three-phase PWM control regester 0 //0x0348
------------------------------------------------------*/
union st_invc0 {            /* union invc0 	   						*/
	struct {            	/* Bit  Access 		   					*/
	 unsigned char 	INV00:1;/* Effective interrupt output polarity select bit */
	 unsigned char 	INV01:1;/* Effective interrupt output specification bit */
	 unsigned char 	INV02:1;/* Mode select bit 						*/
	 unsigned char 	INV03:1;/* Output control bit 					*/
	 unsigned char 	INV04:1;/* Positive and negative phases concurrent L output disable function enable bit */
	 unsigned char 	INV05:1;/* Positive and negative phases concurrent L output detect flag */
	 unsigned char 	INV06:1;/* Modulation mode select bit 			*/
	 unsigned char 	INV07:1;/* Software trigger bit 				*/
	} BIT;   		     	/*        						    	*/
	 unsigned char BYTE;    /*  Byte Access 						*/
};                          /* 						            	*/

/*------------------------------------------------------
    Three-phase PWM control regester 1 //0x0349
------------------------------------------------------*/
union st_invc1 {            /* union invc1 	   							*/
	struct {            	/* Bit  Access 		   						*/
	 unsigned char 	INV10:1;/* Timer Ai start trigger signal select bit */
	 unsigned char 	INV11:1;/* Timer A1-1,A2-1,A4-1 control bit 		*/
	 unsigned char 	INV12:1;/* Short circuit timer count source select bit*/
	 unsigned char 		 :1;/* Nothing Assigned							*/
	 unsigned char 		 :1;/* Reserved bit (always 0)					*/
	 unsigned char 		 :1;/* Nothing Assigned							*/
	 unsigned char 	 	 :1;/* Nothing Assigned							*/
	 unsigned char 		 :1;/* Nothing Assigned							*/
	} BIT;   		     	/*        						    		*/
	unsigned char BYTE;     /*  Byte Access 							*/
};                          /* 						            		*/

/*------------------------------------------------------
    Three-phase output buffer register 0 //0x034a
------------------------------------------------------*/
union st_idb0 {            /* union idb0 	   						*/
	struct {           	   /* Bit  Access 		   					*/
	 unsigned char 	DU0 :1;/* U  phase output buffer 0 				*/
	 unsigned char 	DUB0:1;/* U~ phase output buffer 0 				*/
	 unsigned char 	DV0 :1;/* V  phase output buffer 0 				*/
	 unsigned char 	DVB0:1;/* V~ phase output buffer 0 				*/
	 unsigned char 	DW0 :1;/* W  phase output buffer 0 				*/
	 unsigned char 	DWB0:1;/* W~ phase output buffer 0 				*/
	 unsigned char 		:1;/* Nothing Assigned						*/
	 unsigned char 		:1;/* Nothing Assigned						*/
	} BIT;   		   	   /*        						    	*/
	unsigned char BYTE;    /*  Byte Access 							*/
};                         /* 						            	*/

/*------------------------------------------------------
    Three-phase output buffer register 1 //0x034b
------------------------------------------------------*/
union st_idb1 {            /* union idb1 	   						*/
	struct {	           /* Bit  Access 		   					*/
	 unsigned char 	DU1 :1;/* U  phase output buffer 1				*/
	 unsigned char	DUB1:1;/* U~ phase output buffer 1 				*/
	 unsigned char	DV1 :1;/* V  phase output buffer 1 				*/
	 unsigned char	DVB1:1;/* V~ phase output buffer 1 				*/
	 unsigned char	DW1 :1;/* W  phase output buffer 1 				*/
	 unsigned char	DWB1:1;/* W~ phase output buffer 1 				*/
	 unsigned char		:1;/* Nothing Assigned						*/
	 unsigned char		:1;/* Nothing Assigned						*/
	} BIT;  	 		   /*        						    	*/
	unsigned char BYTE;    /*  Byte Access 							*/
};                         /* 						            	*/

/*----------------------------------------------------------------------------------
   Timer mode registers  //0x035b,0x035c,0x035d,0x0396,
                           0x0397,0x0398,0x0399,0x039a,0x039b,0x039c
---------------------------------------------------------------------------------*/
union st_tmr {               /* union tmr    	   					*/
	struct {             	 /* Bit  Access 		   				*/
	 unsigned char 	TMOD0:1; /* Operation mode select bit 			*/
	 unsigned char	TMOD1:1; /* Operation mode select bit 			*/
	 unsigned char	MR0	 :1; /* Pulse output function select bit	*/
	 unsigned char	MR1  :1; /* External trigger select bit			*/
	 unsigned char	MR2  :1; /* Trigger select bit					*/
	 unsigned char	MR3  :1; /* Must always be "0" in one-shot timer*/
	 unsigned char	TCK0 :1; /* Count source select bit 			*/
	 unsigned char	TCK1 :1; /* Count source select bit 			*/
	} BIT;   		     	 /*       						    	*/
	unsigned char BYTE;      /*  Byte Access 						*/
};

/*------------------------------------------------------
   Interrupt request cause select register 2  //0x035e
------------------------------------------------------*/
union st_ifsr2a {               /* union ifsr2a   	   					*/
	struct {             	 /* Bit  Access 				*/
	 unsigned char 	      :1; /* Nothing assigned			*/
	 unsigned char	      :1; /* Nothing assigned 			*/
	 unsigned char	      :1; /* Nothing assigned    		*/
	 unsigned char	      :1; /* Nothing assigned			*/
	 unsigned char	      :1; /* Nothing assigned			*/
	 unsigned char	      :1; /* Nothing assigned            */
	 unsigned char IFSR26 :1; /* Interrupt request cause select bit */
	 unsigned char IFSR27 :1; /* Interrupt request cause select bit */
	} BIT;   		     	 /*       						    	*/
	unsigned char BYTE;      /*  Byte Access 						*/
};

/*------------------------------------------------------
Interrupt request cause select register //0x035f
-----------------------------------------------------*/
union st_ifsr {              /* union IFSR    	   						*/
	struct {             	 /* Bit  Access 		   					*/
	 unsigned char 	IFSR0:1; /* INT0~ interrupt polarity switching bit  */
	 unsigned char	IFSR1:1; /* INT1~ interrupt polarity switching bit  */
	 unsigned char	IFSR2:1; /* INT2~ interrupt polarity switching bit  */
	 unsigned char	IFSR3:1; /* INT3~ interrupt polarity switching bit  */
	 unsigned char	IFSR4:1; /* INT4~ interrupt polarity switching bit  */
	 unsigned char	IFSR5:1; /* INT5~ interrupt polarity switching bit  */
	 unsigned char	IFSR6:1; /* Interrupt request cause select bit 		*/
	 unsigned char	IFSR7:1; /* Interrupt request cause select bit 		*/
	} BIT;   		     	 /*        						    		*/
	unsigned char BYTE;      /*  Byte Access 							*/
};                           /* 						            	*/

/*------------------------------------------------------
   SI/O4 control registers //0x0360
------------------------------------------------------*/
union st_s4c {              /* union S4C    	   						*/
	struct {   		        /* Bit  Access 		   						*/
	 unsigned char 	SM40:1; /* Internal synchronous clock select bit */
	 unsigned char	SM41:1; /* Internal synchronous clock select bit */
	 unsigned char	SM42:1; /* Sout4 output disable bit */
	 unsigned char	SM43:1; /* SI/O4 port select bit */
	 unsigned char	SM44:1; /* CLK polarity select bit */
	 unsigned char	SM45:1; /* Transfer direction select bit */
	 unsigned char	SM46:1; /* Synchronous clock select bit */
	 unsigned char	SM47:1; /* Sout4 initial value set bit */
	} BIT;   		    	/*        						    		*/
	unsigned char BYTE;     /*  Byte Access 							*/
};

/*------------------------------------------------------

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