sfr6n4.h

基于瑞萨 M16C 的最新版本 IIC 通信

    Three-phase PWM control register 1
------------------------------------------------------*/
union byte_def invc1_addr;
#define     invc1       invc1_addr.byte

#define     inv10       invc1_addr.b.b0     /* Timer A1, A2, A4 start trigger signal select bit */
#define     inv11       invc1_addr.b.b1     /* Timer A1-1, A2-1, A4-1 control bit */
#define     inv12       invc1_addr.b.b2     /* Dead time timer count source select bit */
#define     inv13       invc1_addr.b.b3     /* Carrier wave detect flag */
#define     inv14       invc1_addr.b.b4     /* Output polarity control bit */
#define     inv15       invc1_addr.b.b5     /* Dead time invalid bit */
#define     inv16       invc1_addr.b.b6     /* Dead time timer trigger select bit */

/*------------------------------------------------------
    Three-phase output buffer register 0
------------------------------------------------------*/
union byte_def idb0_addr;
#define     idb0    idb0_addr.byte

#define     du0         idb0_addr.b.b0      /* U phase output buffer 0 */
#define     dub0        idb0_addr.b.b1      /* UB phase output buffer 0 */
#define     dv0         idb0_addr.b.b2      /* V phase output buffer 0 */
#define     dvb0        idb0_addr.b.b3      /* VB phase output buffer 0 */
#define     dw0         idb0_addr.b.b4      /* W phase output buffer 0 */
#define     dwb0        idb0_addr.b.b5      /* WB phase output buffer 0 */

/*------------------------------------------------------
    Three-phase output buffer register 1
------------------------------------------------------*/
union byte_def idb1_addr;
#define     idb1    idb1_addr.byte

#define     du1         idb1_addr.b.b0      /* U phase output buffer 1 */
#define     dub1        idb1_addr.b.b1      /* UB phase output buffer 1 */
#define     dv1         idb1_addr.b.b2      /* V phase output buffer 1 */
#define     dvb1        idb1_addr.b.b3      /* VB phase output buffer 1 */
#define     dw1         idb1_addr.b.b4      /* W phase output buffer 1 */
#define     dwb1        idb1_addr.b.b5      /* WB phase output buffer 1 */

/*------------------------------------------------------
     Dead time timer ; Use "MOV" instruction write to this register.
------------------------------------------------------*/
union byte_def dtt_addr;
#define     dtt     dtt_addr.byte

/*------------------------------------------------------
     Timer B2 interrupt occurrences frequency set counter ; Use "MOV" instruction to write to this register.
------------------------------------------------------*/
union byte_def ictb2_addr;
#define     ictb2   ictb2_addr.byte

/*------------------------------------------------------
    One-shot start flag
------------------------------------------------------*/
union byte_def onsf_addr;
#define     onsf    onsf_addr.byte

#define     ta0os       onsf_addr.b.b0      /* Timer A0 one-shot start flag */
#define     ta1os       onsf_addr.b.b1      /* Timer A1 one-shot start flag */
#define     ta2os       onsf_addr.b.b2      /* Timer A2 one-shot start flag */
#define     ta3os       onsf_addr.b.b3      /* Timer A3 one-shot start flag */
#define     ta4os       onsf_addr.b.b4      /* Timer A4 one-shot start flag */
#define     tazie       onsf_addr.b.b5      /* Z-phase input enable bit */
#define     ta0tgl      onsf_addr.b.b6      /* Timer A0 event/trigger select bit */
#define     ta0tgh      onsf_addr.b.b7      /* Timer A0 event/trigger select bit */

/*------------------------------------------------------
    Clock prescaler reset flag
------------------------------------------------------*/
union byte_def cpsrf_addr;
#define     cpsrf   cpsrf_addr.byte

#define     cpsr        cpsrf_addr.b.b7     /* Clock prescaler reset flag */

/*------------------------------------------------------
    Trigger select register
------------------------------------------------------*/
union byte_def trgsr_addr;
#define     trgsr   trgsr_addr.byte

#define     ta1tgl      trgsr_addr.b.b0     /* Timer A1 event/trigger select bit */
#define     ta1tgh      trgsr_addr.b.b1     /* Timer A1 event/trigger select bit */
#define     ta2tgl      trgsr_addr.b.b2     /* Timer A2 event/trigger select bit */
#define     ta2tgh      trgsr_addr.b.b3     /* Timer A2 event/trigger select bit */
#define     ta3tgl      trgsr_addr.b.b4     /* Timer A3 event/trigger select bit */
#define     ta3tgh      trgsr_addr.b.b5     /* Timer A3 event/trigger select bit */
#define     ta4tgl      trgsr_addr.b.b6     /* Timer A4 event/trigger select bit */
#define     ta4tgh      trgsr_addr.b.b7     /* Timer A4 event/trigger select bit */

/*------------------------------------------------------
    Up/down flag
------------------------------------------------------*/
union byte_def udf_addr;
#define     udf     udf_addr.byte

#define     ta0ud       udf_addr.b.b0       /* Timer A0 up/down flag */
#define     ta1ud       udf_addr.b.b1       /* Timer A1 up/down flag */
#define     ta2ud       udf_addr.b.b2       /* Timer A2 up/down flag */
#define     ta3ud       udf_addr.b.b3       /* Timer A3 up/down flag */
#define     ta4ud       udf_addr.b.b4       /* Timer A4 up/down flag */
#define     ta2p        udf_addr.b.b5       /* Timer A2 two-phase pulse signal processing select bit */
#define     ta3p        udf_addr.b.b6       /* Timer A3 two-phase pulse signal processing select bit */
#define     ta4p        udf_addr.b.b7       /* Timer A4 two-phase pulse signal processing select bit */

/*------------------------------------------------------
    UART transmit/receive control register 2
------------------------------------------------------*/
union byte_def ucon_addr;
#define     ucon    ucon_addr.byte

#define     u0irs       ucon_addr.b.b0      /* UART0 transmit interrupt cause select bit */
#define     u1irs       ucon_addr.b.b1      /* UART1 transmit interrupt cause select bit */
#define     u0rrm       ucon_addr.b.b2      /* UART0 continuous receive mode enable bit */
#define     u1rrm       ucon_addr.b.b3      /* UART1 continuous receive mode enable bit */
#define     clkmd0      ucon_addr.b.b4      /* UART1 CLK/CLKS select bit 0 */
#define     clkmd1      ucon_addr.b.b5      /* UART1 CLK/CLKS select bit 1 */
#define     rcsp        ucon_addr.b.b6      /* Separate UART0 CTS/RTS bit */

/*------------------------------------------------------
    UART2 transmit/receive control register 1
------------------------------------------------------*/
union byte_def u2c1_addr;
#define     u2c1    u2c1_addr.byte

#define     te_u2c1     u2c1_addr.b.b0      /* Transmit enable bit */
#define     ti_u2c1     u2c1_addr.b.b1      /* Transmit buffer empty flag */
#define     re_u2c1     u2c1_addr.b.b2      /* Receive enable bit */
#define     ri_u2c1     u2c1_addr.b.b3      /* Receive complete flag */
#define     u2irs       u2c1_addr.b.b4      /* UART2 transmit interrupt cause select bit */
#define     u2rrm       u2c1_addr.b.b5      /* UART2 continuous receive mode enable bit */
#define     u2lch       u2c1_addr.b.b6      /* Data logic select bit */
#define     u2ere       u2c1_addr.b.b7      /* Error signal output enable bit */

/*------------------------------------------------------
    UART0 special mode register 4
------------------------------------------------------*/
union byte_def u0smr4_addr;
#define     u0smr4          u0smr4_addr.byte

#define     stareq_u0smr4   u0smr4_addr.b.b0    /* Start condition generate bit */
#define     rstareq_u0smr4  u0smr4_addr.b.b1    /* Restart condition generate bit */
#define     stpreq_u0smr4   u0smr4_addr.b.b2    /* Stop condition generate bit */
#define     stspsel_u0smr4  u0smr4_addr.b.b3    /* SCL,SDA output select bit */
#define     ackd_u0smr4     u0smr4_addr.b.b4    /* ACK data bit */
#define     ackc_u0smr4     u0smr4_addr.b.b5    /* ACK data output enable bit */
#define     sclhi_u0smr4    u0smr4_addr.b.b6    /* SCL output stop enable bit */
#define     swc9_u0smr4     u0smr4_addr.b.b7    /* SCL wait bit 3 */

/*------------------------------------------------------
    UART0 special mode register 3
------------------------------------------------------*/
union byte_def u0smr3_addr;
#define     u0smr3          u0smr3_addr.byte

#define     ckph_u0smr3     u0smr3_addr.b.b1    /* Clock phase set bit */
#define     nodc_u0smr3     u0smr3_addr.b.b3    /* Clock output select bit */
#define     dl0_u0smr3      u0smr3_addr.b.b5    /* SDA0 digital delay setup bit */
#define     dl1_u0smr3      u0smr3_addr.b.b6    /* SDA0 digital delay setup bit */
#define     dl2_u0smr3      u0smr3_addr.b.b7    /* SDA0 digital delay setup bit */

/*------------------------------------------------------
    UART0 special mode register 2
------------------------------------------------------*/
union byte_def u0smr2_addr;
#define     u0smr2          u0smr2_addr.byte

#define      iicm2_u0smr2    u0smr2_addr.b.b0   /* I2C mode selection bit 2 */
#define      csc_u0smr2      u0smr2_addr.b.b1   /* Clock-synchronous bit */
#define      swc_u0smr2      u0smr2_addr.b.b2   /* SCL wait output bit */
#define      als_u0smr2      u0smr2_addr.b.b3   /* SDA output stop bit */
#define      stac_u0smr2     u0smr2_addr.b.b4   /* UART0 initialization bit */
#define      swc2_u0smr2     u0smr2_addr.b.b5   /* SCL wait output bit 2 */
#define      sdhi_u0smr2     u0smr2_addr.b.b6   /* SDA output disable bit */

/*------------------------------------------------------
    UART0 special mode register
------------------------------------------------------*/
union byte_def u0smr_addr;
#define     u0smr           u0smr_addr.byte

#define     iicm_u0smr      u0smr_addr.b.b0     /* I2C mode select bit */
#define     abc_u0smr       u0smr_addr.b.b1     /* Arbitration lost detecting flag control bit */
#define     bbs_u0smr       u0smr_addr.b.b2     /* Bus busy flag */
#define     abscs_u0smr     u0smr_addr.b.b4     /* Bus collision detect sampling clock select bit */
#define     acse_u0smr      u0smr_addr.b.b5     /* Auto clear function select bit of transmit enable bit */
#define     sss_u0smr       u0smr_addr.b.b6     /* Transmit start condition select bit */

/*------------------------------------------------------
    UART1 special mode register 4
------------------------------------------------------*/
union byte_def u1smr4_addr;
#define     u1smr4          u1smr4_addr.byte

#define     stareq_u1smr4   u1smr4_addr.b.b0    /* Start condition generate bit */
#define     rstareq_u1smr4  u1smr4_addr.b.b1    /* Restart condition generate bit */
#define     stpreq_u1smr4   u1smr4_addr.b.b2    /* Stop condition generate bit */
#define     stspsel_u1smr4  u1smr4_addr.b.b3    /* SCL,SDA output select bit */
#define     ackd_u1smr4     u1smr4_addr.b.b4    /* ACK data bit */
#define     ackc_u1smr4     u1smr4_addr.b.b5    /* ACK data output enable bit */
#define     sclhi_u1smr4    u1smr4_addr.b.b6    /* SCL output stop enable bit */
#define     swc9_u1smr4     u1smr4_addr.b.b7    /* SCL wait bit 3 */

/*------------------------------------------------------
    UART1 special mode register 3
------------------------------------------------------*/
union byte_def u1smr3_addr;
#define     u1smr3          u1smr3_addr.byte

#define     ckph_u1smr3     u1smr3_addr.b.b1    /* Clock phase set bit */
#define     nodc_u1smr3     u1smr3_addr.b.b3    /* Clock output select bit */
#define     dl0_u1smr3      u1smr3_addr.b.b5    /* SDA1 digital delay setup bit */
#define     dl1_u1smr3      u1smr3_addr.b.b6    /* SDA1 digital delay setup bit */
#define     dl2_u1smr3      u1smr3_addr.b.b7    /* SDA1 digital delay setup bit */

/*------------------------------------------------------
    UART1 special mode register 2
------------------------------------------------------*/
union byte_def u1smr2_addr;
#define     u1smr2          u1smr2_addr.byte

#define     iicm2_u1smr2    u1smr2_addr.b.b0    /* I2C mode selection bit 2 */
#define     csc_u1smr2      u1smr2_addr.b.b1    /* Clock-synchronous bit */
#define     swc_u1smr2      u1smr2_addr.b.b2    /* SCL wait output bit */
#define     als_u1smr2      u1smr2_addr.b.b3    /* SDA output stop bit */
#define     stac_u1smr2     u1smr2_addr.b.b4    /* UART1 initialization bit */
#define     swc2_u1smr2     u1smr2_addr.b.b5    /* SCL wait output bit 2 */
#define     sdhi_u1smr2     u1smr2_addr.b.b6    /* SDA output disable bit */

/*------------------------------------------------------
    UART1 special mode register
------------------------------------------------------*/
union byte_def u1smr_addr;
#define     u1smr           u1smr_addr.byte

#define     iicm_u1smr      u1smr_addr.b.b0     /* I2C mode select bit */
#define     abc_u1smr       u1smr_addr.b.b1     /* Arbitration lost detecting flag control bit */
#define     bbs_u1smr       u1smr_addr.b.b2     /* Bus busy flag */
#define     abscs_u1smr     u1smr_addr.b.b4     /* Bus collision detect sampling clock select bit */
#define     acse_u1smr      u1smr_addr.b.b5     /* Auto clear function select bit of transmit enable bit */
#define     sss_u1smr       u1smr_addr.b.b6     /* Transmit start condition select bit */

/*------------------------------------------------------
    UART2 special mode register 4
------------------------------------------------------*/
union byte_def u2smr4_addr;
#define     u2smr4          u2smr4_addr.byte

#define     stareq_u2smr4   u2smr4_addr.b.b0    /* Start condition generate bit */
#define     rstareq_u2smr4  u2smr4_addr.b.b1    /* Restart condition generate bit */
#define     stpreq_u2smr4   u2smr4_addr.b.b2    /* Stop condition generate bit */
#define     stspsel_u2smr4  u2smr4_addr.b.b3    /* SCL,SDA output select bit */
#define     ackd_u2smr4     u2smr4_addr.b.b4    /* ACK data bit */
#define     ackc_u2smr4     u2smr4_addr.b.b5    /* ACK data output enable bit */
#define     sclhi_u2smr4    u2smr4_addr.b.b6    /* SCL output stop enable bit */
#define     swc9_u2smr4     u2smr4_addr.b.b7    /* SCL wait bit 3 */

/*------------------------------------------------------
    UART2 special mode register 3
------------------------------------------------------*/
union byte_def u2smr3_addr;
#define     u2smr3          u2smr3_addr.byte

#define     ckph_u2smr3     u2smr3_addr.b.b1    /* Clock phase set bit */
#define     nodc_u2smr3     u2smr3_addr.b.b3    /* Clock output select bit */
#define     dl0_u2smr3      u2smr3_addr.b.b5    /* SDA2 digital delay setup bit */
#define     dl1_u2smr3      u2smr3_addr.b.b6    /* SDA2 digital delay setup bit */
#define     dl2_u2smr3      u2smr3_addr.b.b7    /* SDA2 digital delay setup bit */

/*------------------------------------------------------
    UART2 special mode register 2
------------------------------------------------------*/
union byte_def u2smr2_addr;
#define     u2smr2          u2smr2_addr.byte

#define     iicm2_u2smr2    u2smr2_addr.b.b0    /* I2C mode selection bit 2 */