sfr6n4.h

基于瑞萨 M16C 的最新版本 IIC 通信

#pragma ADDRESS     pd4_addr        03eah       /* Port P4 direction register */

#pragma ADDRESS     pd5_addr        03ebh       /* Port P5 direction register */

#pragma ADDRESS     p6_addr         03ech       /* Port P6 register */

#pragma ADDRESS     p7_addr         03edh       /* Port P7 register */

#pragma ADDRESS     pd6_addr        03eeh       /* Port P6 direction register */

#pragma ADDRESS     pd7_addr        03efh       /* Port P7 direction register */

#pragma ADDRESS     p8_addr         03f0h       /* Port P8 register */

#pragma ADDRESS     p9_addr         03f1h       /* Port P9 register */

#pragma ADDRESS     pd8_addr        03f2h       /* Port P8 direction register */

#pragma ADDRESS     pd9_addr        03f3h       /* Port P9 direction register */

#pragma ADDRESS     p10_addr        03f4h       /* Port P10 register */

#pragma ADDRESS     pd10_addr       03f6h       /* Port P10 direction register */

#pragma ADDRESS     pur0_addr       03fch       /* Pull-up control register 0 */

#pragma ADDRESS     pur1_addr       03fdh       /* Pull-up control register 1 */

#pragma ADDRESS     pur2_addr       03feh       /* Pull-up control register 2 */

#pragma ADDRESS     pcr_addr        03ffh       /* Port control register */

/********************************************************
*   declare  SFR char                                   *
********************************************************/
/*------------------------------------------------------
    D-A0 register
------------------------------------------------------*/
unsigned char   da0_addr;
#define     da0     da0_addr

/*------------------------------------------------------
    D-A0 register
------------------------------------------------------*/
unsigned char   da1_addr;
#define     da1     da1_addr

/********************************************************
*   declare SFR bit                                     *
********************************************************/
struct bit_def {
    char    b0:1;
    char    b1:1;
    char    b2:1;
    char    b3:1;
    char    b4:1;
    char    b5:1;
    char    b6:1;
    char    b7:1;
};
union byte_def{
    struct bit_def b;
    char    byte;
};

/*------------------------------------------------------
    Processor mode register 0
------------------------------------------------------*/
union byte_def pm0_addr;
#define     pm0     pm0_addr.byte

#define     pm00        pm0_addr.b.b0       /* Processor mode bit */
#define     pm01        pm0_addr.b.b1       /* Processor mode bit */
#define     pm02        pm0_addr.b.b2       /* R/W mode select bit*/
#define     pm03        pm0_addr.b.b3       /* Software reset bit */
#define     pm04        pm0_addr.b.b4       /* Multiplexed bus space select bit */
#define     pm05        pm0_addr.b.b5       /* Multiplexed bus space select bit */
#define     pm06        pm0_addr.b.b6       /* Port P40 to P43 function select bit */
#define     pm07        pm0_addr.b.b7       /* BCLK output disable bit */

/*------------------------------------------------------
    Processor mode register 1
------------------------------------------------------*/
union byte_def pm1_addr;
#define     pm1     pm1_addr.byte
#define     pm10        pm1_addr.b.b0       /* CS2 area switching bit */
#define     pm11        pm1_addr.b.b1       /* Port P37 to P34 function select bit */
#define     pm12        pm1_addr.b.b2       /* Watchdog timer function select bit */
#define     pm13        pm1_addr.b.b3       /* Internal reserved area expansion bit */
#define     pm17        pm1_addr.b.b7       /* Wait bit */

/*------------------------------------------------------
    System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define     cm0     cm0_addr.byte

#define     cm00        cm0_addr.b.b0       /* Clock output function select bit */
#define     cm01        cm0_addr.b.b1       /* Clock output function select bit */
#define     cm02        cm0_addr.b.b2       /* WAIT peripheral function clock stop bit */
#define     cm03        cm0_addr.b.b3       /* Xcin-Xcout drive capacity select bit */
#define     cm04        cm0_addr.b.b4       /* Port Xc select bit */
#define     cm05        cm0_addr.b.b5       /* Main clock stop bit */
#define     cm06        cm0_addr.b.b6       /* Main clock division select bit 0 */
#define     cm07        cm0_addr.b.b7       /* System clock select bit */

/*------------------------------------------------------
    System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define     cm1     cm1_addr.byte

#define     cm10        cm1_addr.b.b0       /* All clock stop control bit */
#define     cm11        cm1_addr.b.b1       /* System clock select bit 1 */
#define     cm15        cm1_addr.b.b5       /* Xin-Xout drive capacity select bit */
#define     cm16        cm1_addr.b.b6       /* Main clock division select bit 1 */
#define     cm17        cm1_addr.b.b7       /* Main clock division select bit 1 */

/*------------------------------------------------------
    Chip select control register
------------------------------------------------------*/
union byte_def csr_addr;
#define     csr     csr_addr.byte

#define     cs0         csr_addr.b.b0       /* CS0 output enable bit */
#define     cs1         csr_addr.b.b1       /* CS1 output enable bit */
#define     cs2         csr_addr.b.b2       /* CS2 output enable bit */
#define     cs3         csr_addr.b.b3       /* CS3 output enable bit */
#define     cs0w        csr_addr.b.b4       /* CS0 wait bit */
#define     cs1w        csr_addr.b.b5       /* CS1 wait bit */
#define     cs2w        csr_addr.b.b6       /* CS2 wait bit */
#define     cs3w        csr_addr.b.b7       /* CS3 wait bit */

/*------------------------------------------------------
    Address match interrupt enable register
------------------------------------------------------*/
union byte_def aier_addr;
#define     aier    aier_addr.byte

#define     aier0       aier_addr.b.b0      /* Address match interrupt 0 enable bit */
#define     aier1       aier_addr.b.b1      /* Address match interrupt 1 enable bit */

/*------------------------------------------------------
    Address match interrupt enable register
------------------------------------------------------*/
union byte_def aier2_addr;
#define     aier2   aier2_addr.byte

#define     aier20      aier2_addr.b.b0     /* Address match interrupt 2 enable bit */
#define     aier21      aier2_addr.b.b1     /* Address match interrupt 3 enable bit */

/*------------------------------------------------------
    Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define     prcr    prcr_addr.byte

#define     prc0        prcr_addr.b.b0  /* Enables writing to
                                           system clock control register 0,1
                                           CAN clock select register
                                           Peripheral function clock select register */
#define     prc1        prcr_addr.b.b1  /* Enables writing to processor mode register 0,1 */
#define     prc2        prcr_addr.b.b2  /* Enables writing to
                                           port P7/9 direction register
                                           SI/O3 control register */

/*------------------------------------------------------
    Oscillation stop detection register
------------------------------------------------------*/
union byte_def cm2_addr;
#define     cm2     cm2_addr.byte

#define     cm20        cm2_addr.b.b0       /* Oscillation stop, re-oscillation detection enable bit */
#define     cm21        cm2_addr.b.b1       /* System clock select bit 2 */
#define     cm22        cm2_addr.b.b2       /* Oscillation stop, re-oscillation detection flag */
#define     cm23        cm2_addr.b.b3       /* Xin monitor flag */
#define     cm27        cm2_addr.b.b7       /* Operation select bit */

/*------------------------------------------------------
    Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define     wdts    wdts_addr.byte

/*------------------------------------------------------
    Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define     wdc     wdc_addr.byte

#define     wdc7        wdc_addr.b.b7       /* Prescaler select bit */

/*------------------------------------------------------
    Chip select expansion control register
------------------------------------------------------*/
union byte_def cse_addr;
#define     cse         cse_addr.byte

#define     cse00w      cse_addr.b.b0       /* CS0 wait expansion bit */
#define     cse01w      cse_addr.b.b1       /* CS0 wait expansion bit */
#define     cse10w      cse_addr.b.b2       /* CS1 wait expansion bit */
#define     cse11w      cse_addr.b.b3       /* CS1 wait expansion bit */
#define     cse20w      cse_addr.b.b4       /* CS2 wait expansion bit */
#define     cse21w      cse_addr.b.b5       /* CS2 wait expansion bit */
#define     cse30w      cse_addr.b.b6       /* CS3 wait expansion bit */
#define     cse31w      cse_addr.b.b7       /* CS3 wait expansion bit */

/*------------------------------------------------------
    PLL control register 0
------------------------------------------------------*/
union byte_def plc0_addr;
#define     plc0        plc0_addr.byte

#define     plc00       plc0_addr.b.b0      /* PLL multiplying factor select bit */
#define     plc01       plc0_addr.b.b1      /* PLL multiplying factor select bit */
#define     plc02       plc0_addr.b.b2      /* PLL multiplying factor select bit */
#define     plc07       plc0_addr.b.b7      /* Operation enable bit */

/*------------------------------------------------------
    Processor mode register 2
------------------------------------------------------*/
union byte_def pm2_addr;
#define     pm2         pm2_addr.byte

#define     pm20        pm2_addr.b.b0       /* Specifying wait when accessing SFR at PLL operation */
#define     pm22        pm2_addr.b.b2       /* WDT count source protective bit */

/*------------------------------------------------------
    CRC input register
------------------------------------------------------*/
union byte_def crcin_addr;
#define     crcin   crcin_addr.byte

/*------------------------------------------------------
    Count start flag
------------------------------------------------------*/
union byte_def tabsr_addr;
#define     tabsr   tabsr_addr.byte

#define     ta0s        tabsr_addr.b.b0     /* Timer A0 count start flag */
#define     ta1s        tabsr_addr.b.b1     /* Timer A1 count start flag */
#define     ta2s        tabsr_addr.b.b2     /* Timer A2 count start flag */
#define     ta3s        tabsr_addr.b.b3     /* Timer A3 count start flag */
#define     ta4s        tabsr_addr.b.b4     /* Timer A4 count start flag */
#define     tb0s        tabsr_addr.b.b5     /* Timer B0 count start flag */
#define     tb1s        tabsr_addr.b.b6     /* Timer B1 count start flag */
#define     tb2s        tabsr_addr.b.b7     /* Timer B2 count start flag */

/*------------------------------------------------------
    Timer B3,B4,B5 count start flag
------------------------------------------------------*/
union byte_def tbsr_addr;
#define     tbsr    tbsr_addr.byte

#define     tb3s        tbsr_addr.b.b5      /* Timer B3 count start flag */
#define     tb4s        tbsr_addr.b.b6      /* Timer B4 count start flag */
#define     tb5s        tbsr_addr.b.b7      /* Timer B5 count start flag */

/*------------------------------------------------------
    Three-phase PWM control register 0
------------------------------------------------------*/
union byte_def invc0_addr;
#define     invc0   invc0_addr.byte

#define     inv00       invc0_addr.b.b0     /* Effective interrupt output polarity select bit */
#define     inv01       invc0_addr.b.b1     /* Effective interrupt output specification bit */
#define     inv02       invc0_addr.b.b2     /* Mode select bit */
#define     inv03       invc0_addr.b.b3     /* Output control bit */
#define     inv04       invc0_addr.b.b4     /* Positive and negative phases concurrent output disable bit */
#define     inv05       invc0_addr.b.b5     /* Positive and negative phases concurrent output detect flag */
#define     inv06       invc0_addr.b.b6     /* Modulation mode select bit */
#define     inv07       invc0_addr.b.b7     /* Software trigger select bit */

/*------------------------------------------------------