sfr26.h

基于瑞萨 M16C 的最新版本 IIC 通信

/*------------------------------------------------------
   bit
int4ic
------------------------------------------------------*/
union byte_def int4ic_addr;
#define    int4ic        int4ic_addr.byte

#define    ilvl0_int4ic  int4ic_addr.bit.b0
#define    ilvl1_int4ic  int4ic_addr.bit.b1
#define    ilvl2_int4ic  int4ic_addr.bit.b2
#define    ir_int4ic     int4ic_addr.bit.b3
#define    pol_int4ic    int4ic_addr.bit.b4

/*------------------------------------------------------
   bit
int5ic
------------------------------------------------------*/
union byte_def int5ic_addr;
#define    int5ic        int5ic_addr.byte

#define    ilvl0_int5ic  int5ic_addr.bit.b0
#define    ilvl1_int5ic  int5ic_addr.bit.b1
#define    ilvl2_int5ic  int5ic_addr.bit.b2
#define    ir_int5ic     int5ic_addr.bit.b3
#define    pol_int5ic    int5ic_addr.bit.b4

/*------------------------------------------------------
  Timer mode register
------------------------------------------------------*/

/*------------------------------------------------------
   bit
ta0mr
------------------------------------------------------*/
union byte_def ta0mr_addr;
#define    ta0mr        ta0mr_addr.byte

#define    tmod0_ta0mr  ta0mr_addr.bit.b0    /* Operation mode select bit */
#define    tmod1_ta0mr  ta0mr_addr.bit.b1    /* Operation mode select bit */
#define    mr0_ta0mr    ta0mr_addr.bit.b2
#define    mr1_ta0mr    ta0mr_addr.bit.b3
#define    mr2_ta0mr    ta0mr_addr.bit.b4
#define    mr3_ta0mr    ta0mr_addr.bit.b5
#define    tck0_ta0mr   ta0mr_addr.bit.b6     /* Count source select bit */
#define    tck1_ta0mr   ta0mr_addr.bit.b7     /* Count source select bit */

/*------------------------------------------------------
   bit
ta1mr
------------------------------------------------------*/
union byte_def ta1mr_addr;
#define    ta1mr        ta1mr_addr.byte

#define    tmod0_ta1mr  ta1mr_addr.bit.b0    /* Operation mode select bit */
#define    tmod1_ta1mr  ta1mr_addr.bit.b1    /* Operation mode select bit */
#define    mr0_ta1mr    ta1mr_addr.bit.b2
#define    mr1_ta1mr    ta1mr_addr.bit.b3
#define    mr2_ta1mr    ta1mr_addr.bit.b4
#define    mr3_ta1mr    ta1mr_addr.bit.b5
#define    tck0_ta1mr   ta1mr_addr.bit.b6     /* Count source select bit */
#define    tck1_ta1mr   ta1mr_addr.bit.b7     /* Count source select bit */

/*------------------------------------------------------
   bit
ta2mr
------------------------------------------------------*/
union byte_def ta2mr_addr;
#define    ta2mr        ta2mr_addr.byte

#define    tmod0_ta2mr  ta2mr_addr.bit.b0    /* Operation mode select bit */
#define    tmod1_ta2mr  ta2mr_addr.bit.b1    /* Operation mode select bit */
#define    mr0_ta2mr    ta2mr_addr.bit.b2
#define    mr1_ta2mr    ta2mr_addr.bit.b3
#define    mr2_ta2mr    ta2mr_addr.bit.b4
#define    mr3_ta2mr    ta2mr_addr.bit.b5
#define    tck0_ta2mr   ta2mr_addr.bit.b6     /* Count source select bit */
#define    tck1_ta2mr   ta2mr_addr.bit.b7     /* Count source select bit */

/*------------------------------------------------------
   bit
ta3mr
------------------------------------------------------*/
union byte_def ta3mr_addr;
#define    ta3mr        ta3mr_addr.byte

#define    tmod0_ta3mr  ta3mr_addr.bit.b0    /* Operation mode select bit */
#define    tmod1_ta3mr  ta3mr_addr.bit.b1    /* Operation mode select bit */
#define    mr0_ta3mr    ta3mr_addr.bit.b2
#define    mr1_ta3mr    ta3mr_addr.bit.b3
#define    mr2_ta3mr    ta3mr_addr.bit.b4
#define    mr3_ta3mr    ta3mr_addr.bit.b5
#define    tck0_ta3mr   ta3mr_addr.bit.b6     /* Count source select bit */
#define    tck1_ta3mr   ta3mr_addr.bit.b7     /* Count source select bit */

/*------------------------------------------------------
   bit
ta4mr
------------------------------------------------------*/
union byte_def ta4mr_addr;
#define    ta4mr        ta4mr_addr.byte

#define    tmod0_ta4mr  ta4mr_addr.bit.b0    /* Operation mode select bit */
#define    tmod1_ta4mr  ta4mr_addr.bit.b1    /* Operation mode select bit */
#define    mr0_ta4mr    ta4mr_addr.bit.b2
#define    mr1_ta4mr    ta4mr_addr.bit.b3
#define    mr2_ta4mr    ta4mr_addr.bit.b4
#define    mr3_ta4mr    ta4mr_addr.bit.b5
#define    tck0_ta4mr   ta4mr_addr.bit.b6     /* Count source select bit */
#define    tck1_ta4mr   ta4mr_addr.bit.b7     /* Count source select bit */

/*------------------------------------------------------
   bit
tb0mr
------------------------------------------------------*/
union byte_def tb0mr_addr;
#define    tb0mr        tb0mr_addr.byte

#define    tmod0_tb0mr  tb0mr_addr.bit.b0    /* Operation mode select bit */
#define    tmod1_tb0mr  tb0mr_addr.bit.b1    /* Operation mode select bit */
#define    mr0_tb0mr    tb0mr_addr.bit.b2
#define    mr1_tb0mr    tb0mr_addr.bit.b3
#define    mr2_tb0mr    tb0mr_addr.bit.b4
#define    mr3_tb0mr    tb0mr_addr.bit.b5
#define    tck0_tb0mr   tb0mr_addr.bit.b6     /* Count source select bit */
#define    tck1_tb0mr   tb0mr_addr.bit.b7     /* Count source select bit */

/*------------------------------------------------------
   bit
tb1mr
------------------------------------------------------*/
union byte_def tb1mr_addr;
#define    tb1mr        tb1mr_addr.byte

#define    tmod0_tb1mr  tb1mr_addr.bit.b0    /* Operation mode select bit */
#define    tmod1_tb1mr  tb1mr_addr.bit.b1    /* Operation mode select bit */
#define    mr0_tb1mr    tb1mr_addr.bit.b2
#define    mr1_tb1mr    tb1mr_addr.bit.b3
#define    mr2_tb1mr    tb1mr_addr.bit.b4
#define    mr3_tb1mr    tb1mr_addr.bit.b5
#define    tck0_tb1mr   tb1mr_addr.bit.b6     /* Count source select bit */
#define    tck1_tb1mr   tb1mr_addr.bit.b7     /* Count source select bit */

/*------------------------------------------------------
   bit
tb2mr
------------------------------------------------------*/
union byte_def tb2mr_addr;
#define    tb2mr        tb2mr_addr.byte

#define    tmod0_tb2mr  tb2mr_addr.bit.b0    /* Operation mode select bit */
#define    tmod1_tb2mr  tb2mr_addr.bit.b1    /* Operation mode select bit */
#define    mr0_tb2mr    tb2mr_addr.bit.b2
#define    mr1_tb2mr    tb2mr_addr.bit.b3
#define    mr2_tb2mr    tb2mr_addr.bit.b4
#define    mr3_tb2mr    tb2mr_addr.bit.b5
#define    tck0_tb2mr   tb2mr_addr.bit.b6     /* Count source select bit */
#define    tck1_tb2mr   tb2mr_addr.bit.b7     /* Count source select bit */

/*------------------------------------------------------
   bit
ifsr
------------------------------------------------------*/
union byte_def ifsr_addr;
#define    ifsr     ifsr_addr.byte

#define    ifsr0    ifsr_addr.bit.b0    /* INT0 interrupt polarity switching bit */
#define    ifsr1    ifsr_addr.bit.b1    /* INT1 interrupt polarity switching bit */
#define    ifsr3    ifsr_addr.bit.b3    /* INT3 interrupt polarity switching bit */
#define    ifsr4    ifsr_addr.bit.b4    /* INT4 interrupt polarity switching bit */
#define    ifsr5    ifsr_addr.bit.b5    /* INT5 interrupt polarity switching bit */
#define    ifsr6    ifsr_addr.bit.b6    /* Interrupt request cause select bit */
#define    ifsr7    ifsr_addr.bit.b7    /* Interrupt request cause select bit */

/*------------------------------------------------------
  UARTi transmit/receive mode register
------------------------------------------------------*/

/*------------------------------------------------------
   bit
u0mr
------------------------------------------------------*/
union byte_def u0mr_addr;
#define    u0mr         u0mr_addr.byte

#define    smd0_u0mr    u0mr_addr.bit.b0    /* Serial I/O mode select bit */
#define    smd1_u0mr    u0mr_addr.bit.b1    /* Serial I/O mode select bit */
#define    smd2_u0mr    u0mr_addr.bit.b2    /* Serial I/O mode select bit */
#define    ckdir_u0mr   u0mr_addr.bit.b3   /* Internal/external clock select bit */
#define    stps_u0mr    u0mr_addr.bit.b4    /* Stop bit length select bit */
#define    pry_u0mr     u0mr_addr.bit.b5     /* Odd/even parity select bit */
#define    prye_u0mr    u0mr_addr.bit.b6    /* Parity enable bit */

/*------------------------------------------------------
   bit
u1mr
------------------------------------------------------*/
union byte_def u1mr_addr;
#define    u1mr         u1mr_addr.byte

#define    smd0_u1mr    u1mr_addr.bit.b0    /* Serial I/O mode select bit */
#define    smd1_u1mr    u1mr_addr.bit.b1    /* Serial I/O mode select bit */
#define    smd2_u1mr    u1mr_addr.bit.b2    /* Serial I/O mode select bit */
#define    ckdir_u1mr   u1mr_addr.bit.b3   /* Internal/external clock select bit */
#define    stps_u1mr    u1mr_addr.bit.b4    /* Stop bit length select bit */
#define    pry_u1mr     u1mr_addr.bit.b5     /* Odd/even parity select bit */
#define    prye_u1mr    u1mr_addr.bit.b6    /* Parity enable bit */

/*------------------------------------------------------
   bit
u2mr
------------------------------------------------------*/
union byte_def u2mr_addr;
#define    u2mr         u2mr_addr.byte

#define    smd0_u2mr    u2mr_addr.bit.b0    /* Serial I/O mode select bit */
#define    smd1_u2mr    u2mr_addr.bit.b1    /* Serial I/O mode select bit */
#define    smd2_u2mr    u2mr_addr.bit.b2    /* Serial I/O mode select bit */
#define    ckdir_u2mr   u2mr_addr.bit.b3   /* Internal/external clock select bit */
#define    stps_u2mr    u2mr_addr.bit.b4    /* Stop bit length select bit */
#define    pry_u2mr     u2mr_addr.bit.b5     /* Odd/even parity select bit */
#define    prye_u2mr    u2mr_addr.bit.b6    /* Parity enable bit */
#define    iopol_u2mr   u2mr_addr.bit.b7   /* TxD RxD I/O polarity reverse bit */

/*------------------------------------------------------
  UARTi transmit/receive control register 0
------------------------------------------------------*/

/*------------------------------------------------------
   bit
u0c0
------------------------------------------------------*/
union byte_def u0c0_addr;
#define    u0c0         u0c0_addr.byte

#define    clk0_u0c0    u0c0_addr.bit.b0    /* BRG Count source select bit */
#define    clk1_u0c0    u0c0_addr.bit.b1    /* BRG Count source select bit */
#define    crs_u0c0     u0c0_addr.bit.b2     /* CTS~/RTS~ function select bit */
#define    txept_u0c0   u0c0_addr.bit.b3   /* Transmit register empty flag */
#define    crd_u0c0     u0c0_addr.bit.b4     /* CTS~/RTS~ disable bit */
#define    nch_u0c0     u0c0_addr.bit.b5     /* Data output select bit */
#define    ckpol_u0c0   u0c0_addr.bit.b6   /* CLK polarity select bit */
#define    uform_u0c0   u0c0_addr.bit.b7   /* Transfer format select bit */

/*------------------------------------------------------
   bit
u1c0
------------------------------------------------------*/
union byte_def u1c0_addr;
#define    u1c0         u1c0_addr.byte

#define    clk0_u1c0    u1c0_addr.bit.b0    /* BRG Count source select bit */
#define    clk1_u1c0    u1c0_addr.bit.b1    /* BRG Count source select bit */
#define    crs_u1c0     u1c0_addr.bit.b2     /* CTS~/RTS~ function select bit */
#define    txept_u1c0   u1c0_addr.bit.b3   /* Transmit register empty flag */
#define    crd_u1c0     u1c0_addr.bit.b4     /* CTS~/RTS~ disable bit */
#define    nch_u1c0     u1c0_addr.bit.b5     /* Data output select bit */
#define    ckpol_u1c0   u1c0_addr.bit.b6   /* CLK polarity select bit */
#define    uform_u1c0   u1c0_addr.bit.b7   /* Transfer format select bit */

/*------------------------------------------------------
   bit
u2c0
------------------------------------------------------*/
union byte_def u2c0_addr;
#define    u2c0         u2c0_addr.byte

#define    clk0_u2c0    u2c0_addr.bit.b0    /* BRG Count source select bit */
#define    clk1_u2c0    u2c0_addr.bit.b1    /* BRG Count source select bit */
#define    crs_u2c0     u2c0_addr.bit.b2     /* CTS~/RTS~ function select bit */
#define    txept_u2c0   u2c0_addr.bit.b3   /* Transmit register empty flag */
#define    crd_u2c0     u2c0_addr.bit.b4     /* CTS~/RTS~ disable bit */
#define    nch_u2c0     u2c0_addr.bit.b5     /* Data output select bit */
#define    ckpol_u2c0   u2c0_addr.bit.b6   /* CLK polarity select bit */
#define    uform_u2c0   u2c0_addr.bit.b7   /* Transfer format select bit */

/*------------------------------------------------------
  UARTi transmit/receive control register 1
------------------------------------------------------*/

/*------------------------------------------------------
   bit
u0c1
------------------------------------------------------*/
union byte_def u0c1_addr;
#define    u0c1       u0c1_addr.byte

#define    te_u0c1    u0c1_addr.bit.b0    /* Transmit enable bit */
#define    ti_u0c1    u0c1_addr.bit.b1    /* Transmit buffer empty flag */
#define    re_u0c1    u0c1_addr.bit.b2    /* Receive enable bit */
#define    ri_u0c1    u0c1_addr.bit.b3    /* Receive complete flag */

/*------------------------------------------------------
   bit
u1c1
------------------------------------------------------*/
union byte_def u1c1_addr;
#define    u1c1       u1c1_addr.byte

#define    te_u1c1    u1c1_addr.bit.b0    /* Transmit enable bit */
#define    ti_u1c1    u1c1_addr.bit.b1    /* Transmit buffer empty flag */
#define    re_u1c1    u1c1_addr.bit.b2    /* Receive e