sfr26.h

基于瑞萨 M16C 的最新版本 IIC 通信

  struct bit_def bit;
  char  byte;
};

/*------------------------------------------------------
  Processor mode register 0 bit defines
------------------------------------------------------*/
union byte_def pm0_addr;
#define    pm0     pm0_addr.byte

#define    pm00    pm0_addr.bit.b0    /* Processor mode bit */
#define    pm01    pm0_addr.bit.b1    /* Processor mode bit */
#define    pm03    pm0_addr.bit.b3    /* Software reset bit */

/*------------------------------------------------------
  Processor mode register 1 bit defines
------------------------------------------------------*/
union byte_def pm1_addr;
#define    pm1     pm1_addr.byte

#define    pm10    pm1_addr.bit.b0    /* Flash data block access bit. 1= enabled. */
#define    pm12    pm1_addr.bit.b2    /* Watchdog timer function select bit. */
#define    pm17    pm1_addr.bit.b7    /* Wait bit */

/*------------------------------------------------------
  Processor mode register 2 bit defines
------------------------------------------------------*/
union byte_def pm2_addr;
#define    pm2     pm2_addr.byte

#define    pm20    pm2_addr.bit.b0    /* Specifies wait for SFR register access */
#define    pm21    pm2_addr.bit.b1    /* System clock protect bit */
#define    pm22    pm2_addr.bit.b2    /* Watchdog timer count source protect bit */
#define    pm24    pm2_addr.bit.b4    /* P85/NMI configuration bit */

/*------------------------------------------------------
  System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define    cm0     cm0_addr.byte

#define    cm02    cm0_addr.bit.b2    /* WAIT peripheral function clock stop bit */
#define    cm03    cm0_addr.bit.b3    /* Xcin-Xcout drive capacity select bit */
#define    cm04    cm0_addr.bit.b4    /* Port Xc select bit */
#define    cm05    cm0_addr.bit.b5    /* Main clock stop bit */
#define    cm06    cm0_addr.bit.b6    /* Main clock division select bit 0 */
#define    cm07    cm0_addr.bit.b7    /* System clock select bit */

/*------------------------------------------------------
  System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define    cm1     cm1_addr.byte

#define    cm10    cm1_addr.bit.b0    /* All clock stop control bit */
#define    cm15    cm1_addr.bit.b5    /* Xin-Xout drive capacity select bit */
#define    cm16    cm1_addr.bit.b6    /* Main clock division select bit 0 */  
#define    cm17    cm1_addr.bit.b7    /* Main clock division select bit 1 */  

/*------------------------------------------------------
  Peripheral clock select register
------------------------------------------------------*/
union byte_def pclkr_addr;
#define    pclkr    pclkr_addr.byte

#define    pclk0    pclkr_addr.bit.b0    /* Timer A, B, clock source select bit */
#define    pclk1    pclkr_addr.bit.b1    /* SI/O clock source select bit */

/*------------------------------------------------------
  Oscillation stop detection register
------------------------------------------------------*/
union byte_def cm2_addr;
#define    cm2     cm2_addr.byte

#define    cm20    cm2_addr.bit.b0    /* Oscillation stop detection bit */
#define    cm21    cm2_addr.bit.b1    /* Main clock switch bit */
#define    cm22    cm2_addr.bit.b2    /* Oscillation stop detection status */
#define    cm23    cm2_addr.bit.b3    /* Clock monitor bit */
#define    cm27    cm2_addr.bit.b7    /* Operation select bit */

/*------------------------------------------------------
  Power supply detection register 1
------------------------------------------------------*/
union byte_def vcr1_addr;
#define    vcr1     vcr1_addr.byte

#define    vc13     vcr1_addr.bit.b3    /* Vdet4 power supply monitor flag */
/*------------------------------------------------------
  Power supply detection register 2
------------------------------------------------------*/
union byte_def vcr2_addr;
#define    vcr2     vcr2_addr.byte

#define    vc25     vcr2_addr.bit.b5    /* Power supply Vdet2 enable and monitor bit */
#define    vc26     vcr2_addr.bit.b6    /* Power supply Vdet3 enable and monitor bit */
#define    vc27     vcr2_addr.bit.b7    /* Power supply Vdet4 enable and monitor bit */

/*------------------------------------------------------
  Power supply Vdet4 detection register
------------------------------------------------------*/
union byte_def d4int_addr;
#define    d4int    d4int_addr.byte

#define    d40      d4int_addr.bit.b0    /* Vdet4 detection interrupt enable bit */
#define    d41      d4int_addr.bit.b1    /* STOP mode deactivation control bit */
#define    d42      d4int_addr.bit.b2    /* Vdet4 up/down detection flag */
#define    d43      d4int_addr.bit.b3    /* WDT overflow detection flag */
#define    df0      d4int_addr.bit.b4    /* Sampling clock select bit 0 */
#define    df1      d4int_addr.bit.b5    /* Sampling clock select bit 1 */

/*------------------------------------------------------
  Addrese match interrupt enable register
------------------------------------------------------*/
union byte_def aier_addr;
#define    aier     aier_addr.byte

#define    aier0    aier_addr.bit.b0    /* Address match interrupt 0 enable bit */
#define    aier1    aier_addr.bit.b1    /* Address match interrupt 1 enable bit */

/*------------------------------------------------------
  Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define    prcr    prcr_addr.byte

#define    prc0    prcr_addr.bit.b0    /* Enables writing to PCLKR, CM0, CM1 and CM2 registers */
#define    prc1    prcr_addr.bit.b1    /* Enables writing to INVC0, INVC1, TB2SC, PM0, PM1 and PM2 registers */
#define    prc2    prcr_addr.bit.b2    /* Enables writing to PD9 register */
#define    prc3    prcr_addr.bit.b3    /* Enables writing to VCR2 and D4INT registers */

/*------------------------------------------------------
  Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define    wdts    wdts_addr.byte

/*------------------------------------------------------
  Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define    wdc     wdc_addr.byte

#define    wdc5    wdc_addr.bit.b5    /* Cold/warm start discrimination flag */
#define    wdc7    wdc_addr.bit.b7    /* Prescaler select bit */

/*------------------------------------------------------
  Count start flag
------------------------------------------------------*/
union byte_def tabsr_addr;
#define    tabsr   tabsr_addr.byte

#define    ta0s    tabsr_addr.bit.b0    /* Timer A0 count start flag */
#define    ta1s    tabsr_addr.bit.b1    /* Timer A1 count start flag */
#define    ta2s    tabsr_addr.bit.b2    /* Timer A2 count start flag */
#define    ta3s    tabsr_addr.bit.b3    /* Timer A3 count start flag */
#define    ta4s    tabsr_addr.bit.b4    /* Timer A4 count start flag */
#define    tb0s    tabsr_addr.bit.b5    /* Timer B0 count start flag */
#define    tb1s    tabsr_addr.bit.b6    /* Timer B1 count start flag */
#define    tb2s    tabsr_addr.bit.b7    /* Timer B2 count start flag */

/*------------------------------------------------------
  Three-phase PWM control register 0
------------------------------------------------------*/
union byte_def invc0_addr;
#define    invc0    invc0_addr.byte

#define    inv00    invc0_addr.bit.b0    /* Effective interrupt output polarity select bit */
#define    inv01    invc0_addr.bit.b1    /* Effective interrupt output specification bit */
#define    inv02    invc0_addr.bit.b2    /* Mode select bit */
#define    inv03    invc0_addr.bit.b3    /* Output control bit */
#define    inv04    invc0_addr.bit.b4    /* Positive and negative phases concurrent L output disable function enable bit */
#define    inv05    invc0_addr.bit.b5    /* Positive and negative phases concurrent L output detect flag */
#define    inv06    invc0_addr.bit.b6    /* Modulation mode select bit */
#define    inv07    invc0_addr.bit.b7    /* Software trigger bit */

/*------------------------------------------------------
  Three-phase PWM control register 1
------------------------------------------------------*/
union byte_def invc1_addr;
#define    invc1    invc1_addr.byte

#define    inv10    invc1_addr.bit.b0    /* Timer A1, A2 and A4 start trigger signal */
#define    inv11    invc1_addr.bit.b1    /* Timer A1-1, A2-1, A4-1 control bit */
#define    inv12    invc1_addr.bit.b2    /* Dead time timer count source select bit */
#define    inv13    invc1_addr.bit.b3    /* Carrier wave detect flag */
#define    inv14    invc1_addr.bit.b4    /* Output polarity control bit */
#define    inv15    invc1_addr.bit.b5    /* Dead time invalid bit */
#define    inv16    invc1_addr.bit.b6    /* Dead time timer trigger select bit */
#define    inv17    invc1_addr.bit.b7    /* Waveform reflect timing select bit */

/*------------------------------------------------------
  Three-phase output buffer register 0
------------------------------------------------------*/
union byte_def idb0_addr;
#define    idb0     idb0_addr.byte

#define    du0      idb0_addr.bit.b0    /* U  phase output buffer 0 */
#define    dub0     idb0_addr.bit.b1    /* U~ phase output buffer 0 */
#define    dv0      idb0_addr.bit.b2    /* V  phase output buffer 0 */
#define    dvb0     idb0_addr.bit.b3    /* V~ phase output buffer 0 */
#define    dw0      idb0_addr.bit.b4    /* W  phase output buffer 0 */
#define    dwb0     idb0_addr.bit.b5    /* W~ phase output buffer 0 */

/*------------------------------------------------------
  Three-phase output buffer register 1
------------------------------------------------------*/
union byte_def idb1_addr;
#define    idb1     idb1_addr.byte

#define    du1      idb1_addr.bit.b0    /* U  phase output buffer 1  */
#define    dub1     idb1_addr.bit.b1    /* U~ phase output buffer 1  */
#define    dv1      idb1_addr.bit.b2    /* V  phase output buffer 1  */
#define    dvb1     idb1_addr.bit.b3    /* V~ phase output buffer 1  */
#define    dw1      idb1_addr.bit.b4    /* W  phase output buffer 1  */
#define    dwb1     idb1_addr.bit.b5    /* W~ phase output buffer 1  */

/*------------------------------------------------------
   Dead timer timer
------------------------------------------------------*/
union byte_def dtt_addr;
#define    dtt      dtt_addr.byte

/*------------------------------------------------------
   Timer B2 interrupt occurrences frequency set counter
------------------------------------------------------*/
union byte_def ictb2_addr;
#define    ictb2    ictb2_addr.byte

/*------------------------------------------------------
  Timer B2 special mode register
------------------------------------------------------*/
union byte_def tb2sc_addr;
#define     tb2sc   tb2sc_addr.byte

#define     pwcon   tb2sc_addr.bit.b0    /* Timer B2 reload timing switching bit  */
#define     ivpcr1  tb2sc_addr.bit.b1    /* Three phase output port NMI control bit 1 */

/*------------------------------------------------------
  One-shot start flag
------------------------------------------------------*/
union byte_def onsf_addr;
#define    onsf       onsf_addr.byte

#define    ta0os      onsf_addr.bit.b0    /* Timer A0 one-shot start flag */
#define    ta1os      onsf_addr.bit.b1    /* Timer A1 one-shot start flag */
#define    ta2os      onsf_addr.bit.b2    /* Timer A2 one-shot start flag */
#define    ta3os      onsf_addr.bit.b3    /* Timer A3 one-shot start flag */
#define    ta4os      onsf_addr.bit.b4    /* Timer A4 one-shot start flag */
#define    ta0tgl     onsf_addr.bit.b6    /* Timer A0 event/trigger select bit */
#define    ta0tgh     onsf_addr.bit.b7    /* Timer A0 event/trigger select bit */

/*------------------------------------------------------
  Clock prescaler reset flag
------------------------------------------------------*/
union byte_def cpsrf_addr;
#define    cpsrf      cpsrf_addr.byte

#define    cpsr       cpsrf_addr.bit.b7    /* Clock prescaler reset flag */

/*------------------------------------------------------
  Trigger select register
------------------------------------------------------*/
union byte_def trgsr_addr;
#define    trgsr     trgsr_addr.byte

#define    ta1tgl    trgsr_addr.bit.b0    /* Timer A1 event/trigger select bit */
#define    ta1tgh    trgsr_addr.bit.b1    /* Timer A1 event/trigger select bit */
#define    ta2tgl    trgsr_addr.bit.b2    /* Timer A2 event/trigger select bit */
#define    ta2tgh    trgsr_addr.bit.b3    /* Timer A2 event/trigger select bit */
#define    ta3tgl    trgsr_addr.bit.b4    /* Timer A3 event/trigger select bit */
#define    ta3tgh    trgsr_addr.bit.b5    /* Timer A3 event/trigger select bit */
#define    ta4tgl    trgsr_addr.bit.b6    /* Timer A4 event/trigger select bit */
#define    ta4tgh    trgsr_addr.bit.b7    /* Timer A4 event/trigger select bit */

/*------------------------------------------------------
  Up/down flag
------------------------------------------------------*/
union byte_def udf_addr;
#define    udf      udf_addr.byte

/*------------------------------------------------------
  UART transmit/receive control register 2
------------------------------------------------------*/
union byte_def ucon_addr;
#define    ucon       ucon_addr.byte

#define    u0irs      ucon_addr.bit.b0    /* UART0 transmit interrupt cause select bit */
#define    u1irs      ucon_addr.bit.b1    /* UART1 transmit interrupt cause select bit */
#define    u0rrm      ucon_addr.bit.b2    /* UART0 continuous receive mode enable bit */
#define    u1rrm      ucon_addr.bit.b3    /* UART1 continuous receive mode enable bit */
#define    clkmd0     ucon_addr.bit.b4    /* CLK/CLKS select bit 0 */
#define    clkmd1     ucon_addr.bit.b5    /* CLK/CLKS select bit 1 */
#define    rcsp       ucon_addr.bit.b6    /* Separate CTS~/RTS~ bit */

/*------------------------------------------------------
  UART2 transmit/receive control register 1
------------------------------------------------------*/
union byte_def u2c1_addr;
#define    u2c1       u2c1_addr.byte

#define    te_u2c1    u2c1_addr.bit.b0    /* Transmit enable bit */
#define    ti_u2c1    u2c1_addr.bit.b1    /* Transmit buffer empty flag */
#define    re_u2c1    u2c1_addr.bit.b2    /* Receive enable bit */
#define    ri_u2c1    u2c1_addr.bit.b3    /* Receive complete flag */
#define    u2irs      u2c1_addr.bit.b4    /* UART2 transmit interrupt cause select bit */
#define    u2rrm      u2c1_addr.bit.b5    /* UART2 continuous receive mode enable bit */