mmu.s

来自「arm7的嵌入式系统ucos2移植」· S 代码 · 共 100 行

;*****************************************************************************
;
; MMU.S - Builds the MMU page table.
;
; Copyright (c) 1999 Cirrus Logic, Inc.
;
;*****************************************************************************

;OLD_BOARD EQU 0

;*****************************************************************************
;
; The MMU page table.  The virtual memory map created by this page table
; is as follows:
;
;     0x00000000 - 0x0001ffff => 128K of program ROM (nCS0)
;     0x00020000 - 0x00029fff => 40K of internal SRAM (only 37.5K exists)
;     0x0002a000 - 0x0002afff => NAND FLASH interface (nCS1)
;     0x0002b000 - 0x0002bfff => Parallel port interface (nCS1)
;     0x0002c000 - 0x0002ffff => EP7209 internal registers
;
;*****************************************************************************

    GBLA    XCount

;*****************************************************************************
;
; PageTable is the level 1 page table.  This really should have all 4K entries
; populated, but we simply populate the first entry since that is all we use.
; Unpredictable results will occur if the program inadvertently accesses a
; memory location past 1Meg.
;
;*****************************************************************************

    AREA    |Assembly$$PageTable_|, DATA, READONLY, ALIGN=14

    EXPORT  PageTable
PageTable
    DCD     Level2 + 0x00000011

;*****************************************************************************
;
; Level2 is the level 2 page table.  This maps all the memory in the system
; that is used by the application into a small 192K block of memory.  As for
; the level 1 page table, we do not populate the entire 256 entries of this
; table...unpredictable results will occur if the program inadvertently access
; a memory location past 192K.
;
;*****************************************************************************

    AREA    |Assembly$$PageTable|, DATA, READONLY, ALIGN=10

Level2
;
; 128K of program ROM, cached
;
XCount SETA 0x00000ffa
    WHILE   XCount < 0x00020000
    DCD     XCount
XCount SETA XCount + 0x00001000
    WEND

;
; 40K of internal SRAM, cached, write buffered
;
XCount SETA 0x60000ffe
    WHILE   XCount < 0x6000a000
    DCD     XCount
XCount SETA XCount + 0x00001000
    WEND

;
; NAND FLASH interface
;
    IF (:DEF: OLD_BOARD)
    DCD     0x10010ff2
    ELSE
    DCD     0x10000ff2
    ENDIF

;
; Parallel port interface
;
    IF (:DEF: OLD_BOARD)
    DCD     0x10000ff2
    ELSE
    DCD     0x30000ff2
    ENDIF

;
; 16K of EP7209 internal registers
;
XCount SETA 0x80000ff2
    WHILE   XCount < 0x80004000
    DCD     XCount
XCount SETA XCount + 0x00001000
    WEND

    END