memmap.s

arm单片机的ucos2移植

	TTL     Memory map for target-specific MMU initialisation    > memmap.s
	; ---------------------------------------------------------------------
	; This file provides the memory map table for MMU initialisation 
	; for the SA-1100 Prospector board. The SETUP_MMU macro references this
	; table to build the TLBs on power-up.
	;
	; $Revision: 1.5 $
	;   $Author: mwelsh $
	;     $Date: 1999/08/02 15:31:35 $
	;
	; Copyright ARM Limited, 1998.
	; All Rights Reserved
	;

	INCLUDE bits.s
	INCLUDE sizes.s
	INCLUDE	platform.s
	INCLUDE	mmu_h.s

	EXPORT	uHAL_AddressTable
	EXPORT	uHAL_MappingTable

RAM12Size	EQU	(RAM1Size + RAM2Size)

	; Note: Table must end with all zeros
	; WindowsCE uses a table of the same format, but without the access
	; word. If OEMAddressTable exists, but uHAL_Level1Table doesn't, the
	; MMU setup code should use the truncated format.
	;
	; MMU Mapping tables of the format:
	;
	; Virtual Address, Physical Address, Access Permissions, Area Size

	AREA    |C$$code$$__mmutable|, CODE, READONLY

	LTORG

uHAL_MappingTable
	DCD	0,	0,	0,	0	; End of Table (MUST BE ZEROS!)

uHAL_AddressTable
	; Map RAM sequential starting from DRAM_BASE, cachable & bufferable
	DCD	DRAM_BASE           , RAM1Base, DRAM_ACCESS, RAM1Size
	DCD	DRAM_BASE+RAM1Size  , RAM2Base, DRAM_ACCESS, RAM2Size

	; Also do 1-1 virtual to physical, bufferable but not cachable
	DCD	RAM1Base, RAM1Base, NCDRAM_ACCESS, RAM1Size
	DCD	RAM2Base, RAM2Base, NCDRAM_ACCESS, RAM2Size

	; PCMCIA Space & External Config Register in ROM4 space
	DCD	PCMCIABase, PCMCIABase, IO_ACCESS, PCMCIASize
	DCD	ROM4Base  , ROM4Base  , IO_ACCESS, SZ_1M
	
	; SA-1100 register Space
	DCD	IOBase, IOBase, IO_ACCESS, IOSize

	; PLD register Space
	DCD	PLD_BASE, PLD_BASE, IO_ACCESS, SZ_1M

	; DCache single-cycle clean space
	DCD	CLEAN_BASE, CLEAN_BASE, DRAM_ACCESS, SZ_1M

	; Map flash very simply
	DCD	FLASH_BASE, ROM1Base, FLASH_ACCESS, FLASH_SIZE
	
        ;; Map FPGA space in ROM4 space, 1-1 mapping
	DCD	ROM2Base, ROM2Base, IO_ACCESS, SZ_64M
        
	; Level 2 areas are more complex to define: 
	; Virt Addr, L2 Table & type, Phys Addr + L2 Access Perms, Area Size
	;DCD	FLASH_BASE, Level2tab_FLASH + EPROM_PAGE 
	;DCD		FLASH_BASE + EPROM_ACCESS, FLASH_SIZE

	DCD	0,	0,	0,	0	; End of Table (MUST BE ZEROS!)

	END