jdcoefct.c

基于Linux的ffmepg decoder

      //#endif
          
      #ifdef VPE_OUTPUT
      //MCU_num++;
      //RTL_DEBUG_OUT(0x98000000 | MCU_num) // show the current MCU_num
      //if(MCU_num==0x6b3) // debug usage
        //printf("MCU Column Number : %d\n",MCU_col_num);
      #endif
      
      
      // DMA stage
      if(stage_active[2])
        {
          //check the control register write operation is done , borrowed from Winnie and Robert
		  FA526_DrainWriteBuffer();
		  
		  
		  POLL_DMA_DONE_START_MARKER
          while(!(pmdma->Status & 0x1)) // check DMA status until DMA stage is done
            ;
          POLL_DMA_DONE_END_MARKER
            
          // stage[2] is done, we made it inactive
          stage_active[2]=FALSE; 

          //#ifdef VPE_OUTPUT
          //RTL_DEBUG_OUT(0x94000000 | 0xc) // signal that DMA engine is done
          //#endif
        }
      
      // DQ-MC stage
      if(stage_active[1])
        {
          m[2]=m[1];
          
          //check the control register write operation is done , borrowed from Winnie and Robert
		  FA526_DrainWriteBuffer();
          
          POLL_MC_DONE_START_MARKER
          // if the DQ_MC stage is active, we need to check whether the DQ_MC is done or not
          do {
	        READ_CPSTS(cpsts_reg)
	      } while(!(cpsts_reg&0x02));
		  POLL_MC_DONE_END_MARKER		  
		  
          //#ifdef VPE_OUTPUT
          //RTL_DEBUG_OUT(0x94000000 | 0xa) // signal that De-Quantization & MC engine is done
          //#endif

          // OK! MC is done, we just start the DMA procedure and activate the stage[2]
          // and store necessary DMA command chain table (to fill eack blocks System Memory Base Address)
          generate_dma_chain_table (cinfo,m[2],pCodec->buf_descriptor2);
          
          // start DMA and activate stage[2]
          #ifdef CORE_VERSION_1            
            pmdma->SMaddr = pCodec->pSDMA_phy;  //pmdma->SMaddr = pCodec->DMA_COMMAND_system;
		    pmdma->LMaddr = pCodec->pLDMA+pCodec->buf_descriptor2*40;
		    pmdma->BlkWidth = 0;		    
		    pmdma->CCA = (unsigned int) pCodec->pSDMA_phy; //pmdma->CCA = (unsigned int) pCodec->DMA_COMMAND_system;
		    pmdma->Control =  (0x04B00000 | (cinfo->blocks_in_MCU)*4); //start DMA and move DMA command buffers from local memory to system memory
		  #elif defined(CORE_VERSION_2)
		    // we can even don't set the SMaddr,LMaddr and BlkWidth DMA register, since
		    // we will start the DMA just right from the local memory and it is enough 
		    // to just set CCA and Control DMA registers.
//		    pmdma->CCA = (unsigned int) (pCodec->pLDMA+pCodec->buf_descriptor2*40) | 0x02;
		    pmdma->CCA = (unsigned int) (DMA_COMMAND_LOCAL_ADDR+pCodec->buf_descriptor2*40*4) | 0x02;
		    pmdma->Control =  (0x04A00000); //start DMA from local memory		    
          #else
            #error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"
          #endif
          //#ifdef VPE_OUTPUT
          //RTL_DEBUG_OUT(0x94000000 | 0xb) // signal that DMA engine has started
          //#endif
          
          stage_active[2]=TRUE;
          stage_active[1]=FALSE; // stage[1] is done, we made it inactive
        }

      // start VLD-DZ Engine and set the VLD-DZ Di-zigzag scan buffer
      if(stage_active[0])
        { 
          int action;
          //MCU_num_DQ_MC++; // mainly used for debug usage
          //if(MCU_num_DQ_MC==0x6b2) // used for debug usage
          //  MCU_num_DQ_MC=MCU_num_DQ_MC; // used for debug usage
            
          m[1]=m[0];
          
          //if(!cinfo->invalid_next_restart_marker && start_vld_flag)
          if(!cinfo->invalid_next_restart_marker)          
          {
            //check the control register write operation is done , borrowed from Winnie and Robert
  		    FA526_DrainWriteBuffer();
            
            POLL_VLD_DONE_START_MARKER
            // check VLD is done or not
            do {
	          READ_VLDSTS(vldsts_reg)
	        } while(!(vldsts_reg&0x01));	        
			POLL_VLD_DONE_END_MARKER
		  }

          //#ifdef VPE_OUTPUT
          //RTL_DEBUG_OUT(0x94000000 | 3) // signal that VLD engine is done
          //#endif
          
          // READ_BADR(v)  // for debug usage
          // READ_VADR(s)  // for debug usage
          // last_bit=(s&0x001f); // for debug usage
          // bitlen=(8-(last_bit%8))%8; // for debug usage
          // SET_BALR(0) // for debug usage

          // BTW, we should check the error code in VLD Status Register since it may contain
          // error if VLD fail
          // Error Code Field for JPEG Hardware: 
          //           value 0 represents 'No Error'
          //           value 7 represents 'Decode DC Error'
          //           value 8 represents 'Decode AC Error'
          // according to software C model, we don't have to take care of such VLD error
          // if we have the restart marker
          // READ_VLDSTS(vldsts_reg)
          // vldsts_reg=((vldsts_reg & 0x0f000)>>12);
          // switch(vldsts_reg)
          //  {
          //    case 0x0: break; // no error
          //    case 0x07:  break; // decode dc error ERREXIT(cinfo, JWRN_HUFF_BAD_CODE);
          //    case 0x08:  break; // decode ac error ERREXIT(cinfo, JWRN_HUFF_BAD_CODE);
          //    default : break; // other unknown error ERREXIT(cinfo, JWRN_HUFF_BAD_CODE);
          //  }
          //}          

          // since the VLD is done, we should decrement the restart_to_go counter in entropy struct
          decrement_restart_interval(cinfo);
          
          //check_restart_marker(cinfo);
          //reset_previous_DC(cinfo);
          action=check_restart_marker(cinfo);
          if(action) // means some actions for restart marker should be taken
            {
              int c=7; // let's loop for advancing restart marker 7 times at most if it is action 2
              // action 1: discard marker and let entropy decoder resume processing
              // action 2: search next marker, to advance
              // action 3: return without advancing past this marker. Entropy decoder
              //           will be forced to process an empty segment.
              do {
                if(action==1) break;
                else if(action==2)
                  {
                    // research and advance the restart marker
                    READ_VLDCTL(vldctl_reg)
                    vldctl_reg=(vldctl_reg&0x0fffffff0)|0x9; // set the command for JPEG search re-sync marker before decoding
                    SET_VLDCTL(vldctl_reg)
                    
                    READ_QAR(dzar_qar)
                    dzar_qar = ((dzar_qar & 0x0000ffff) | ((unsigned int)(pCodec->pingpong_buf[pCodec->buf_descriptor1])) << 16);
                    SET_QAR(dzar_qar) // set the de-zigzag Scan Buffer Address
          
                    // start VLD Engine , to set the MC Control Register's DEC_GO field
                    SET_MCCTL(start_VLD) //set JPEG_mode and DEC_GO and INTRA
                    
                    // check VLD is done or not
                    POLL_VLD_DONE_START_MARKER
                    // check VLD is done or not
                    do {
	                  READ_VLDSTS(vldsts_reg)
	                } while(!(vldsts_reg&0x01));	                
			        POLL_VLD_DONE_END_MARKER
			        action=get_restart_action(cinfo);
                  }
                else if(action==3)
                  { cinfo->invalid_next_restart_marker=TRUE; break; }
                else 
                  break;
              } while(c-- && action);
            }
            
          update_next_restart_number(cinfo);          

          // switch output buffer for DQ-MC Engine
          pCodec->buf_descriptor2^=1; // toggle buffer selection for DQ-MC output buffer
          mciaddr_ptr = (unsigned int *)(CUR_B0 + pCodec->buf_descriptor2 * STRIDE_MCU);		  
          
          // assign QAR register to the pCodec->pingpong_buf[pCodec->buf_descriptor1] as the input buffer of De-Quantization & MC Engine
          READ_QAR(dzar_qar)
          dzar_qar = ((dzar_qar & 0x0ffff0000) | ((unsigned int)pCodec->pingpong_buf[pCodec->buf_descriptor1]));
          SET_QAR(dzar_qar) // set the Quantization Local Buffer Address
          
          //#ifdef VPE_OUTPUT
          //RTL_DEBUG_OUT(0x94000000 | 0x8) // signal that QAR register is set
          //RTL_DEBUG_OUT(0x90000000 | (unsigned int)pCodec->pingpong_buf[pCodec->buf_descriptor1]) // output the QAR value
          //#endif

          // start DQ-MC Engine
		  SET_MCIADDR(mciaddr_ptr)         
          SET_MCCTL(start_DQ_MC)   //set JPEG_mode and DMC_GO and INTRA
          
          //#ifdef VPE_OUTPUT
          //RTL_DEBUG_OUT(0x94000000 | 9) // signal that De-Quantization & MC engine starts
          //#endif

          // activate stage[1]
          stage_active[1]=TRUE;
          stage_active[0]=FALSE; // since VLD engine is done, we made it inactive          
        }

      if(MCU_col_num <= last_MCU_col) // that means there are more MCUs for VLD Engine
        {
          boolean restart_flag=FALSE; // to locally signal the restart situation
          //MCU_num_VLD++; // mainly used for debug usage
          //if(MCU_num_VLD==0x6b2) // used for debug usage
          //  MCU_num_VLD=MCU_num_VLD; // used for debug usage
          
          // READ_BADR(v) // for debug usage
          // READ_VADR(s) // for debug usage
          // last_bit=(s&0x001f); // for debug usage
          // bitlen=(8-(last_bit%8))%8; // for debug usage
          // SET_BALR(0) // for debug usage
                    
          //#ifdef VPE_OUTPUT
          //RTL_DEBUG_OUT(0x94000000 | 0x1) // signal that DZAR register is set
          //RTL_DEBUG_OUT(0x90000000 | (unsigned int)pingpong_buf[buf_descriptor1]) // output the DZAR value
          //#endif
          
          if (processing_restart_marker(cinfo))
            {	
              // the restart interval is reached, and we need to instruct the VLD engine to research the restart marker
              // just set the VLD Control Register's command
              READ_VLDCTL(vldctl_reg)
              vldctl_reg=(vldctl_reg&0x0fffffff0)|0x9; // set the command for JPEG search re-sync marker before decoding
              SET_VLDCTL(vldctl_reg)
              restart_flag=TRUE;
            }
          else
            { // restore back to normal decoding
              // just set the VLD Control Register's command to normal decoding
              READ_VLDCTL(vldctl_reg)
              vldctl_reg=(vldctl_reg&0x0fffffff0)|0x8; // set the command for JPEG normal decoding
              SET_VLDCTL(vldctl_reg)
            }
          
          m[0]=MCU_col_num;
          
          if(!cinfo->invalid_next_restart_marker)
            {
              // switch output buffer for VLD Engine
              pCodec->buf_descriptor1^=1;
            }
              
          // set output buffer for VLD-DZ Engine by setting DZAR register
          READ_QAR(dzar_qar)
          dzar_qar = ((dzar_qar & 0x0000ffff) | ((unsigned int)(pCodec->pingpong_buf[pCodec->buf_descriptor1])) << 16);
          SET_QAR(dzar_qar) // set the de-zigzag Scan Buffer Address
          
          if(!cinfo->invalid_next_restart_marker)
            {
              // start VLD Engine , to set the MC Control Register's DEC_GO field
              SET_MCCTL(start_VLD) //set JPEG_mode and DEC_GO and INTRA
            }
            
          if(cinfo->invalid_next_restart_marker && restart_flag)
            {
              cinfo->invalid_next_restart_marker=FALSE;
            }

          //#ifdef VPE_OUTPUT
          //RTL_DEBUG_OUT(0x94000000 | 2) // signal that VLD engine is started
          //#endif                    
          stage_active[0]=TRUE;
        }
      else // no more MCU for VLD engine, we just make the VLD stage inactive
        stage_active[0]=FALSE;
    }
    
#endif // end of #ifdef USE_INTERNAL_CPU

  return JPEG_ROW_COMPLETED;
}

/*
 * Dummy consume-input routine for single-pass operation.
 */

METHODDEF(int)
dummy_consume_data (j_decompress_ptr cinfo)
{
  return JPEG_SUSPENDED;	/* Always indicate nothing was done */
}


#ifdef D_MULTISCAN_FILES_SUPPORTED

/*
 * Consume input data and store it in the full-image coefficient buffer.
 * We read as much as one fully interleaved MCU row ("iMCU" row) per call,
 * ie, v_samp_factor block rows for each component in the scan.
 * Return value is JPEG_ROW_COMPLETED, JPEG_SCAN_COMPLETED, or JPEG_SUSPENDED.
 */

METHODDEF(int)
consume_data (j_decompress_ptr cinfo)
{
  return JPEG_REACHED_EOI;
  
  /* original code
  my_coef_ptr coef = (my_coef_ptr) cinfo->coef;
  JDIMENSION MCU_col_num;	// index of current MCU within row
  int blkn, ci, xindex, yindex, yoffset;
  JDIMENSION start_col;
  JBLOCKARRAY buffer[MAX_COMPS_IN_SCAN];
  JBLOCKROW buffer_ptr;
  jpeg_component_info *compptr;

  // Align the virtual buffers for the components used in this scan.
  for (ci = 0; ci < cinfo->comps_in_scan; ci++) {