📄 ftmcp100.h
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#define MCCADDR (0x10020 + pCodec->pCoreBaseAddr)
#define MEIADDR (0x10024 + pCodec->pCoreBaseAddr)
#define CPSTS (0x10028 + pCodec->pCoreBaseAddr)
#define QCR_0 (0x1002c + pCodec->pCoreBaseAddr)
#define QCR_1 (0x10030 + pCodec->pCoreBaseAddr)
#define QCR_2 (0x10034 + pCodec->pCoreBaseAddr)
#define QAR (0x10038 + pCodec->pCoreBaseAddr)
#define CKR (0x1003c + pCodec->pCoreBaseAddr)
#define ACDCPAR (0x10040 + pCodec->pCoreBaseAddr)
#define VOADR (0x10044 + pCodec->pCoreBaseAddr)
#define CURDEV (0x10048 + pCodec->pCoreBaseAddr)
#define BADR (0x1004c + pCodec->pCoreBaseAddr)
#define BALR (0x10050 + pCodec->pCoreBaseAddr)
#define MCIADDR (0x10058 + pCodec->pCoreBaseAddr)
#define VLDCTL (0x1005c + pCodec->pCoreBaseAddr)
#define VLDSTS (0x10074 + pCodec->pCoreBaseAddr)
#define ASADR (0x10078 + pCodec->pCoreBaseAddr)
#elif defined(CORE_VERSION_2)
#define MDMA1 ((volatile MDMA *)( 0x20400 + pCodec->pCoreBaseAddr))
#define MECTL (0x20000 + pCodec->pCoreBaseAddr)
#define MEPMV (0x20004 + pCodec->pCoreBaseAddr)
#define MECR (0x20008 + pCodec->pCoreBaseAddr)
#define MIN_SADMV (0x2000c + pCodec->pCoreBaseAddr)
#define CMDADDR (0x20010 + pCodec->pCoreBaseAddr)
#define MECADDR (0x20014 + pCodec->pCoreBaseAddr)
#define HOFFSET (0x20018 + pCodec->pCoreBaseAddr)
#define MCCTL (0x2001c + pCodec->pCoreBaseAddr)
#define MCCADDR (0x20020 + pCodec->pCoreBaseAddr)
#define MEIADDR (0x20024 + pCodec->pCoreBaseAddr)
#define CPSTS (0x20028 + pCodec->pCoreBaseAddr)
#define QCR_0 (0x2002c + pCodec->pCoreBaseAddr)
#define QCR_1 (0x20030 + pCodec->pCoreBaseAddr)
#define QCR_2 (0x20034 + pCodec->pCoreBaseAddr)
#define QAR (0x20038 + pCodec->pCoreBaseAddr)
#define CKR (0x2003c + pCodec->pCoreBaseAddr)
#define ACDCPAR (0x20040 + pCodec->pCoreBaseAddr)
#define VOADR (0x20044 + pCodec->pCoreBaseAddr)
#define CURDEV (0x20048 + pCodec->pCoreBaseAddr)
#define BADR (0x2004c + pCodec->pCoreBaseAddr)
#define BALR (0x20050 + pCodec->pCoreBaseAddr)
#define MVXYD (0x20054 + pCodec->pCoreBaseAddr)
#define MCIADDR (0x20058 + pCodec->pCoreBaseAddr)
#define VLDCTL (0x2005c + pCodec->pCoreBaseAddr)
#define VLDSTS (0x20074 + pCodec->pCoreBaseAddr)
#define ASADR (0x20078 + pCodec->pCoreBaseAddr)
#define VOPSIZE (0x20080 + pCodec->pCoreBaseAddr)
#define PMVBUF (0x20084 + pCodec->pCoreBaseAddr)
#else
#error "Please define the hardware core version (either CORE_VERSION_1 or CORE_VERSION_2)"
#endif
#define READ_CPSTS(v) v=*(volatile unsigned long*)CPSTS; // coprocessor status register
#define READ_VOADR(v) v=*(volatile unsigned long*)VOADR;
#define READ_MIN_SADMV(v) v=*(volatile unsigned long*)MIN_SADMV;
#define READ_CURDEV(v) v=*(volatile unsigned long*)CURDEV;
#define READ_BALR(v) v=*(volatile unsigned long*)BALR;
#define READ_VLDSTS(v) v=*(volatile unsigned long*)VLDSTS;
#define READ_ASADR(v) v=*(volatile unsigned long*)ASADR;
#define SET_BADR(v) *(volatile unsigned long*)BADR=v;
#define SET_BALR(v) *(volatile unsigned long*)BALR=v;
#define SET_MCCADDR(v) *(volatile unsigned long*)MCCADDR=v; // MC current block start address register
#define SET_QAR(v) *(volatile unsigned long*)QAR=v; // Quantization block address register
#define SET_CKR(v) *(volatile unsigned long*)CKR=v;
#define SET_MEIADDR(v) *(volatile unsigned long*)MEIADDR=v; // ME interpolation block start address register
#define SET_CMDADDR(v) *(volatile unsigned long*)CMDADDR=v;
#define SET_MECADDR(v) *(volatile unsigned long*)MECADDR=v; // ME current block start address register
#define SET_ACDCPAR(v) *(volatile unsigned long*)ACDCPAR=v; // ACDC Predictor Buffer Address Register
#define SET_VOADR(v) *(volatile unsigned long*)VOADR=v;
#define SET_MCIADDR(v) *(volatile unsigned long*)MCIADDR=v;
#define SET_QCR_0(v) *(volatile unsigned long*)QCR_0=v;
#define SET_QCR_1(v) *(volatile unsigned long*)QCR_1=v;
#define SET_QCR_2(v) *(volatile unsigned long*)QCR_2=v;
#define SET_MCCTL(v) *(volatile unsigned long*)MCCTL=v;
#define SET_HOFFSET(v) *(volatile unsigned long*)HOFFSET=v; // Horizontal offset to reference block address
#define SET_MECR(v) *(volatile unsigned long*)MECR=v;
#define SET_MEPMV(v) *(volatile unsigned long*)MEPMV=v;
#define SET_MECTL(v) *(volatile unsigned long*)MECTL=v; // ME Control Register
#define SET_VLDCTL(v) *(volatile unsigned long*)VLDCTL=v;
#define SET_ASADR(v) *(volatile unsigned long*)ASADR=v;
#define SET_MVXYD(v) *(volatile unsigned long*)MVXYD=v;
#define SET_VOPSIZE(v) *(volatile unsigned long*)VOPSIZE=v;
#define SET_PMVBUF(v) *(volatile unsigned long*)PMVBUF=v;
#endif
*/
//---------------------------------------------------------------------------
/**************** bank 1 *****************************************/
#define CUR_Y0 0x4000
#define CUR_U0 0x4100
#define CUR_V0 0x4140
#define CUR_Y1 0x4180
#define CUR_U1 0x4280
#define CUR_V1 0x42c0
#define INTER_Y0 0x4300
#define INTER_U0 0x4400
#define INTER_V0 0x4440
#define INTER_Y1 0x4480
#define INTER_U1 0x4580
#define INTER_V1 0x45c0
#define INTER_Y2 0x4600
#define INTER_U2 0x4700
#define INTER_V2 0x4740
/**************** bank 0 *****************************************/
// ME engine will copy the current image to the local buffer space
// pointed by CUR_Y2,CUR_U2,CUR_V2
#define CUR_Y2 0x000
#define CUR_U2 0x100
#define CUR_V2 0x140
/**************** bank 2/3 *****************************************/
// reference image's local buffer
#define REF_Y 0x8000
#define REF_U 0x8c00
#define REF_V 0x8f00
/**************** local predictor buffer *****************************************/
// local ac dc predictor buffer used to communicate with MC engine
#define LOCAL_PREDICTOR0 (0x600) // the 0th entry in local predictor buffer
#define LOCAL_PREDICTOR8 (0x700) // the 8th entry in local predictor buffer
/**************** autobuffer address *****************************************/
#define RUN_LEVEL (0xc00)
#ifdef CORE_VERSION_2
// pmv buffer address for hardware ME engine
#define PMV_BUF (0x1400)
#endif
#define MAX_XDIM 1920
#define MAX_YDIM 1080
#define CKR_RATIO 0
//---------------------------------------------------------------------------
// mainly used for RTL debug port output and marker output
//#define ENABLE_RTL_MONITOR
// the POLL_MARKER_* was used to set a marker for verilog
// simulation debug and waveform observation purpose by
// setting QCR_2 register which is not used in MPEG4 firmware
#if (defined(RTL_PLATFORM) && defined(ENABLE_RTL_MONITOR))
#define POLL_MARKER_S SET_QCR_2(0x00)
#define POLL_MARKER_E SET_QCR_2(0x01)
#define POLL_MC_DONE_MARKER_START SET_QCR_2(0x02)
#define POLL_MC_DONE_MARKER_END SET_QCR_2(0x03)
#define POLL_ME_DONE_MARKER_START SET_QCR_2(0x04)
#define POLL_ME_DONE_MARKER_END SET_QCR_2(0x05)
#define POLL_PMV_DONE_MARKER_START SET_QCR_2(0x06)
#define POLL_PMV_DONE_MARKER_END SET_QCR_2(0x07)
#define POLL_MARKER1_START SET_QCR_2(0x08)
#define POLL_MARKER1_END SET_QCR_2(0x09)
#else
#define POLL_MARKER_S
#define POLL_MARKER_E
#define POLL_MC_DONE_MARKER_START
#define POLL_MC_DONE_MARKER_END
#define POLL_ME_DONE_MARKER_START
#define POLL_ME_DONE_MARKER_END
#define POLL_PMV_DONE_MARKER_START
#define POLL_PMV_DONE_MARKER_END
#define POLL_MARKER1_START
#define POLL_MARKER1_END
#endif
#define VPE 0x90180000
#if (defined(RTL_PLATFORM) && defined(ENABLE_RTL_MONITOR))
#define RTL_DEBUG_OUT(v) *(unsigned int*)VPE=v;
#else
#define RTL_DEBUG_OUT(v)
#endif
//---------------------------------------------------------------------------
#ifndef LINUX
#define WRITE_BUFFER_SYNC __asm { MCR p15, 0, 0, c7, c10, 4}
#endif
//---------------------------------------------------------------------------
#ifdef LINUX
#define FA526_DrainWriteBuffer()
#define FA526_CleanInvalidateDCacheAll()
#else
static __inline void FA526_DrainWriteBuffer(void)
{
unsigned int tmp=0;
__asm { MCR p15,0,tmp,c7,c10,4 }
}
static __inline void FA526_CleanInvalidateDCacheAll()
{
unsigned int tmp=0;
__asm { MCR p15,0,tmp,c7,c14,0 }
}
#endif
//---------------------------------------------------------------------------
typedef struct {
unsigned char *pCoreBaseAddr;
void * pfnDmaMalloc; // The function pointer to user-defined DMA memory allocation function.
void * pfnDmaFree; // The function pointer to user-defined DMA free allocation function.
unsigned int *DMA_COMMAND_local;
unsigned int *ME_command_queue0;
#ifdef CORE_VERSION_1
unsigned int *DMA_COMMAND_system_phy;
unsigned int *DMA_COMMAND_system_virt;
#endif
short *pred_value_phy;
short *pred_value_virt;
// motion estimation related variables
#ifdef CORE_VERSION_1
unsigned int SRC_X[2];
unsigned int SRC_Y[2];
unsigned int tmp_command[3];
unsigned int cmd0, cmd4, cmd8, cmd12, cmd16, cmd20;
#endif
int MVZ;
unsigned int MB_mode; // use Inter if MB_mode == 1
unsigned int ME_COMMAND;
unsigned int even_odd_1; // even_odd_1 was used to control the selection bewteen (CUR_Y0,CUR_U0,CUR_V0) buffer and (CUR_Y1,CUR_U1,CUR_V1) buffer
unsigned int even_odd_I; // even_odd_I was used to control the selection bewteen LOCAL_PREDICTOR0 's double buffers
unsigned char triple_buffer_selector;
int Raddr;
int Raddr23;
unsigned int acdc_status; // acdc_status is number to fill in the field of mcctl register
// some hidden encoding parameters
unsigned int RC_AVERAGE_PERIOD;
unsigned int DELAY_FACTOR;
unsigned int ARG_RC_BUFFER;
} FTMCP100_CODEC;
//---------------------------------------------------------------------------
#endif
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