lcd.h

s3c2410中的lcd驱动代码

#define LDIC_COLMOD_REG             0x3A
#define LDIC_MTPPRO_REG             0x3F
#define LDIC_RGBCTR_REG             0xB0
#define LDIC_FRMCTR1_REG            0xB1
#define LDIC_FRMCTR2_REG            0xB2
#define LDIC_FRMCTR3_REG            0xB3
#define LDIC_INVCTR_REG             0xB4
#define LDIC_RGBBPCTR_REG           0xB5
#define LDIC_DISSET5_REG            0xB6
#define LDIC_VSYNCOUT_REG           0xBC
#define LDIC_VSYNCIN_REG            0xBD
#define LDIC_PWCTR1_REG             0xC0
#define LDIC_PWCTL2_REG             0xC1
#define LDIC_PWCTL3_REG             0xC2
#define LDIC_PWCTL4_REG             0xC3
#define LDIC_PWCTL5_REG             0xC4
#define LDIC_VMCTR1_REG             0xC5
#define LDIC_VMCTR2_REG             0xC6
#define LDIC_WRID1_REG              0xD0
#define LDIC_WRID2_REG              0xD1
#define LDIC_WRID3_REG              0xD2
#define LDIC_RDID1_REG              0xDA
#define LDIC_RDID2_REG              0xDB
#define LDIC_RDID3_REG              0xDC
#define LDIC_RDMTP_REG              0xDE
#define LDIC_PRGMTP_REG             0xDF
#define LDIC_GMCTRP1_REG            0xE0
#define LDIC_GMCTRN1_REG            0xE1
#elif defined(LCD_TM240320LNFWUGWA5)
//5TODO:LCD MODULE DEFINE.
#define LDIC_CHIPREVID_REG      0x00
#define LDIC_MODESEL_REG        0x02
#define LDIC_VBP_REG            0x03
#define LDIC_HBP_REG            0x04
#define LDIC_PARSLO_REG         0x05
#define LDIC_PARSHI_REG         0x06
#define LDIC_PARELO_REG         0x07
#define LDIC_PAREHI_REG         0x08
#define LDIC_DISCTRL1_REG       0x09
#define LDIC_RESET_REG          0x0A
#define LDIC_DISCTRL2_REG       0x7F
#elif defined(LCD_ILI9320DS)
#define LDIC_OSC_REG            0x00
#define LDIC_OUTCTRL_REG        0x01
#define LDIC_WAVECTRL_REG       0x02
#define LDIC_ENTRYMODE_REG      0x03
#define LDIC_RESIZE_REG         0x04
#define LDIC_DISPCTRL1_REG      0x07
#define LDIC_DISPCTRL2_REG      0x08
#define LDIC_DISPCTRL3_REG      0x09
#define LDIC_DISPCTRL4_REG      0x0A
#define LDIC_RGBCTRL1_REG       0x0C
#define LDIC_FMP_REG            0x0D
#define LDIC_RGBCTRL2_REG       0x0F
#define LDIC_PWCTL1_REG         0x10
#define LDIC_PWCTL2_REG         0x11
#define LDIC_PWCTL3_REG         0x12
#define LDIC_PWCTL4_REG         0x13
#define LDIC_GRAMHADD_REG       0x20
#define LDIC_GRAMVADD_REG       0x21
#define LDIC_WRGRAM_REG         0x22
#define LDIC_RDGRAM_REG         0x22
#define LDIC_PWCTL7_REG         0x29
#define LDIC_FRCC_REG           0x2B
#define LDIC_GAMCTL1_REG        0x30
#define LDIC_GAMCTL2_REG        0x31
#define LDIC_GAMCTL3_REG        0x32
#define LDIC_GAMCTL4_REG        0x33
#define LDIC_GAMCTL5_REG        0x34
#define LDIC_GAMCTL6_REG        0x35
#define LDIC_GAMCTL7_REG        0x36
#define LDIC_GAMCTL8_REG        0x37
#define LDIC_GAMCTL9_REG        0x38
#define LDIC_GAMCTL10_REG       0x39
#define LDIC_GAMCTL11_REG       0x3C
#define LDIC_GAMCTL12_REG       0x3D
#define LDIC_HSA_REG            0x50
#define LDIC_HEA_REG            0x51
#define LDIC_VSA_REG            0x52
#define LDIC_VEA_REG            0x53
#define LDIC_GSCTL1_REG         0x60
#define LDIC_GSCTL2_REG         0x61
#define LDIC_GSCTL3_REG         0x6A
#define LDIC_PTD1_REG           0x80
#define LDIC_PTS1_REG           0x81
#define LDIC_PTE1_REG           0x82
#define LDIC_PTD2_REG           0x83
#define LDIC_PTS2_REG           0x84
#define LDIC_PTE2_REG           0x85
#define LDIC_PICTL1_REG         0x90  
#define LDIC_PICTL2_REG         0x92
#define LDIC_PICTL3_REG         0x93
#define LDIC_PICTL4_REG         0x95
#define LDIC_PICTL5_REG         0x97
#define LDIC_PICTL6_REG         0x98

//ILI9320DS SPI Interfase start byte define.Makeup as following(MSB):
// 01110 + ID(1) + RS + RW
#define LDIC_STARTBYTE_IDBITS   0x1D
#define LDIC_STARTBYTE_IDXWRITE     ((LDIC_STARTBYTE_IDBITS << 2) | (0 << 1) | 0)
#define LDIC_STARTBYTE_STATUSREAD   ((LDIC_STARTBYTE_IDBITS << 2) | (0 << 1) | 1) 
#define LDIC_STARTBYTE_CMDWRITE     ((LDIC_STARTBYTE_IDBITS << 2) | (1 << 1) | 0)
#define LDIC_STARTBYTE_CMDREAD      ((LDIC_STARTBYTE_IDBITS << 2) | (1 << 1) | 1)

#elif defined(LCD_LGDP4531)
#define LDIC_OSC_REG            0x00
#define LDIC_OUTCTL1_REG        0x01
#define LDIC_WAVECTRL_REG       0x02
#define LDIC_ENTRYMODE_REG      0x03
#define LDIC_RESIZE_REG         0x04
#define LDIC_DISPCTRL1_REG      0x07
#define LDIC_DISPCTRL2_REG      0x08
#define LDIC_DISPCTRL3_REG      0x09
#define LDIC_DISPCTRL4_REG      0x0A
#define LDIC_DICTRL1_REG        0x0C
#define LDIC_FMP_REG            0x0D
#define LDIC_DICTRL2_REG        0x0F
#define LDIC_PWCTL1_REG         0x10
#define LDIC_PWCTL2_REG         0x11
#define LDIC_PWCTL3_REG         0x12
#define LDIC_PWCTL4_REG         0x13
#define LDIC_REGUCTRL_REG       0x15
#define LDIC_IPSCTRL_REG        0x16
#define LDIC_GRAMHADD_REG       0x20
#define LDIC_GRAMVADD_REG       0x21
#define LDIC_WRGRAM_REG         0x22
#define LDIC_RDGRAM_REG         0x22
#define LDIC_GAMCTL1_REG        0x30
#define LDIC_GAMCTL2_REG        0x31
#define LDIC_GAMCTL3_REG        0x32
#define LDIC_GAMCTL4_REG        0x33
#define LDIC_GAMCTL5_REG        0x34
#define LDIC_GAMCTL6_REG        0x35
#define LDIC_GAMCTL7_REG        0x36
#define LDIC_GAMCTL8_REG        0x37
#define LDIC_GAMCTL9_REG        0x38
#define LDIC_GAMCTL10_REG       0x39
#define LDIC_EPROMCTRL1_REG     0x40
#define LDIC_EPROMCTRL2_REG     0x41
#define LDIC_EPROMCTRL3_REG     0x42
#define LDIC_HSA_REG            0x50
#define LDIC_HEA_REG            0x51
#define LDIC_VSA_REG            0x52
#define LDIC_VEA_REG            0x53
#define LDIC_OUTCTL2_REG        0x60
#define LDIC_BASEIMGCTRL_REG    0x61
#define LDIC_VSCTRL_REG         0x6A
#define LDIC_PARDISPOS1_REG     0x80
#define LDIC_PHAS1_REG          0x81
#define LDIC_PHES1_REG          0x82
#define LDIC_PARDISPOS2_REG     0x83
#define LDIC_PHAS2_REG          0x84
#define LDIC_PHES2_REG          0x85
#define LDIC_PICTL1_REG         0x90
#define LDIC_PICTL2_REG         0x92
#define LDIC_PICTL3_REG         0x93
#define LDIC_PICTL4_REG         0x95
#define LDIC_PICTL5_REG         0x97
#define LDIC_PICTL6_REG         0x98
#define LDIC_TEST1_REG          0xA0
#define LDIC_TEST2_REG          0xA1
#define LDIC_TEST3_REG          0xA2
//LGDP4531 SPI Interfase start byte define.Makeup as following(MSB):
// 01110 + ID(0) + RS + RW
#define LDIC_STARTBYTE_IDBITS   0x1C
#define LDIC_STARTBYTE_IDXWRITE     ((LDIC_STARTBYTE_IDBITS << 2) | (0 << 1) | 0)
#define LDIC_STARTBYTE_STATUSREAD   ((LDIC_STARTBYTE_IDBITS << 2) | (0 << 1) | 1) 
#define LDIC_STARTBYTE_CMDWRITE     ((LDIC_STARTBYTE_IDBITS << 2) | (1 << 1) | 0)
#define LDIC_STARTBYTE_CMDREAD      ((LDIC_STARTBYTE_IDBITS << 2) | (1 << 1) | 1)

#elif defined(LCD_TMT035DNAHCWD)
//5TODO:LCD MODULE DEFINE.

#else
#error "ERROR: Unknown project define." __FILE__
#endif

// TFT timing parameter for V16C6448AB(PRIME VIEW) 
#if defined(LCD_TD028TTEC1)
#define    LCD_XSIZE_TFT           (480)   
#define    LCD_YSIZE_TFT           (640)

#define    LCD_VBPD                (2-1)
#define    LCD_VFPD                (4-1)
#define    LCD_VSPW                (2-1)

#define    LCD_HBPD                (8-1)
#define    LCD_HFPD                (64-1)
#define    LCD_HSPW                (8-1)

#define    LCD_VCLK                 (22000000)

#elif defined(LCD_L4F00242T05)
#define    LCD_XSIZE_TFT           (480)   
#define    LCD_YSIZE_TFT           (640)

#define    LCD_VBPD                (10-1)
#define    LCD_VFPD                (5-1)
#define    LCD_VSPW                (10-1)

#define    LCD_HBPD                (60-1)
#define    LCD_HFPD                (41-1)
#define    LCD_HSPW                (20-1)

#define    LCD_VCLK                 (22000000)

#elif defined(LCD_BM240320_4252FTGAN)
#define    LCD_XSIZE_TFT           (240)   
#define    LCD_YSIZE_TFT           (320)

#define    LCD_VBPD                (2-1)
#define    LCD_VFPD                (16-1)
#define    LCD_VSPW                (2-1)

#define    LCD_HBPD                (4-1)
#define    LCD_HFPD                (15-1)
#define    LCD_HSPW                (5-1)

#define    LCD_VCLK                (5000000)

#elif defined(LCD_TM240320LNFWUGWA5)
#define    LCD_XSIZE_TFT           (240)   
#define    LCD_YSIZE_TFT           (320)

#define    LCD_VBPD                (3-1)
#define    LCD_VFPD                (2-1)
#define    LCD_VSPW                (2-1)

#define    LCD_HBPD                (30-1)
#define    LCD_HFPD                (10-1)
#define    LCD_HSPW                (10-1)

#define    LCD_VCLK                (6300000)      // 70Hz fix noise bug
//#define    LCD_VCLK                (5480000)    //58Hz
#elif defined(LCD_TMT035DNAHCWD)
//5TODO:TM QVGA 3.5 TIMING DEFINE.
#elif defined(LCD_ST7787)
#define    LCD_XSIZE_TFT           (240)   
#define    LCD_YSIZE_TFT           (320)

#define    LCD_VBPD                (2-1)
#define    LCD_VFPD                (16-1)
#define    LCD_VSPW                (2-1)

#define    LCD_HBPD                (4-1)
#define    LCD_HFPD                (15-1)
#define    LCD_HSPW                (5-1)   

#define    LCD_VCLK                (6700000)     //82Hz 

#elif defined(LCD_ILI9320DS)
#define    LCD_XSIZE_TFT           (240)   
#define    LCD_YSIZE_TFT           (320)

#define    LCD_VBPD                (3-1)
#define    LCD_VFPD                (2-1)
#define    LCD_VSPW                (2-1)

#define    LCD_HBPD                (27-1)
#define    LCD_HFPD                (20-1)
#define    LCD_HSPW                (2-1)

#define    LCD_VCLK                (6000000)    //64Hz

#elif defined(LCD_LGDP4531)
#define    LCD_XSIZE_TFT           (240)   
#define    LCD_YSIZE_TFT           (320)

#define    LCD_VBPD                (3-1)
#define    LCD_VFPD                (2-1)
#define    LCD_VSPW                (2-1)

#define    LCD_HBPD                (27-1)
#define    LCD_HFPD                (20-1)
#define    LCD_HSPW                (2-1)

#define    LCD_VCLK                (6000000)    //64Hz

#else
#error "ERROR: Unknown project define." __FILE__
#endif

#define    LCD_HOZVAL_TFT          (LCD_XSIZE_TFT-1)
#define    LCD_LINEVAL_TFT         (LCD_YSIZE_TFT-1)

#define    LCD_ARRAY_SIZE_TFT_16BIT    (LCD_XSIZE_TFT*2*LCD_YSIZE_TFT)


#define     M5D(n)                  ((n)&0x1fffff)

typedef struct {
    u8 comm_addr;
    #if defined(LCD_TD028TTEC1)||defined(LCD_ST7787)||defined(LCD_ILI9320DS)||defined(LCD_LGDP4531)
    u16 conf_data;
    u8 count;
    #elif defined(LCD_L4F00242T05)
    u32 conf_data;
    u8 count;
    #else
    u8 conf_data;
    #endif
} LCD_CONFIG_DATA;

static LCD_CONFIG_DATA Conf_data[] =
{
#if defined(LCD_TD028TTEC1)
    {0x00, 0x00, 0},    //Deep Sleep Release 1
    {0xff, 1, 0},       //delay 1ms
    {0x00, 0x00, 0},    //Deep Sleep Release 2
    {0xff, 1, 0},       //delay 1ms
    {0x00, 0x00, 0},    //Deep Sleep Release 3
    {0xff, 1 , 0},      //delay 1ms
    {0xB0, 0x17, 1},    //Deep Sleep Out
    {0xff, 10, 0},      //delay 10ms

    /*Sleep Out */
    {0xBC, 0X80, 1},    //RGB I/F ON RAM Write OFF QVGA through, SIGCON Enable
    {0xB0, 0X16, 1},    //ACDD ON ,XVDD ON
    {0xB8, 0xFFF9, 2},  //Output control
    {0x11, 0x00, 0},    //Sleep Out
    {0xff, 10, 0},
        
    /*Initial Setting*/
    {0xBF, 0x10, 1},    //Driver system change control
    {0xB1, 0x5A, 1},    //Booster operation setup
    {0xB5, 0x34, 1},    //VCS voltage adjustment
    {0xB6, 0x68, 1},    //VCOM voltage adjustment
    {0xB9, 0x04, 1},    //DCCLK and DCEV timing setup
    {0xBD, 0x00, 1},    //ASW signal slew rate adjustment
    {0xC7,0x7437,2},    //Gamma 1 fine tuning (1)
    {0xC8,0x22,1},    //Gamma 1 fine tuning (2)
    {0xCA,0xA4,1},    //Gamma 1 blue offset adjustment
    {0xEC, 0x0230, 2},  //Total number of horizontal clock sycles
    {0xD2, 0x1400, 2},  //CKV 1,2 timing control
    {0xD3, 0x1A0F, 2},  //OEV timing control
    {0xD4, 0x05A4, 2},  //ASW timing control (1)
    {0xD5, 0x05, 1},    //ASW timing control (2)

#elif defined(LCD_L4F00242T05)
    {LDIC_MADCTL_CMD, 0x00, 1},    //Set  the accessing orders of RAM and the scanning orders of RGB interface.
    {LDIC_GAMSET_CMD, 0x01, 1},    //ASW timing control (2)
    {LDIC_COLMOD_CMD, 0x60, 1},    //Set color mode to 666 mode
    {LDIC_PASET_CMD, 0x0000009F, 4},    //set the page address limits of RAM. Start page is 0d(0000h), End page is 159d(009Fh).
    {LDIC_CASET_CMD, 0x000001DF, 4},    //set the column address limits of RAM. Start column is 0d(0000h), End column is 479d(01DFh).

#elif defined(LCD_BM240320_4252FTGAN)
    //POWER SETTING
    {LDIC_OSCCTL1_REG, 0x51/*0x41*/},  //osc on frequency control +0%,
    {0xff, 50}, //delay 50ms
    {LDIC_PWRCTL6_REG, 0x80/*0x40*/}, //BT=0100 vgh setting
    {LDIC_PWRCTL3_REG, 0x46/*0x44*/}, //VC2=100,VC1=100 DDVDH CONTROL vcil control VR2 control SET DDVDH 5.15-5.19V
    {LDIC_PWRCTL4_REG, 0x00/*0x01*/}, //vc=000 VREG3 ADJUST, AFFECT VGL
    {LDIC_PWRCTL5_REG, 0x03/*0x00*0x06*/}, //vrh=0110
    {LDIC_VCOMCTL2_REG, 0x2f/*0x40*0x31/*0x43*/}, //vcm=1011010 set vcomh
    {LDIC_VCOMCTL3_REG, 0x08/*0x09/*0x0b/*0x0e0x12*/}, //vdv=10001
    {0xff, 10},
    {LDIC_PWRCTL2_REG, 0x04}, //ap=100
    {0xff, 20},
    {LDIC_PWRCTL1_REG, 0x10/*0x18*/}, //gas=0 pon=1 dk=0 xdk=0
    {0xff, 40},
    {LDIC_PWRCTL1_REG, 0x10}, //GASENB=0,PON=1,DK=0,XDK=0,C1 ON 2Xvci;C2 ON;STB off;ddvdh 5.17v
    {0xff, 100},
    {LDIC_VCOMCTL1_REG, 0x80}, //VCOMG=1 vdv adjust disable

    //DISPLAY ON SETTING
    {LDIC_DISPLAYCLT9_REG, 0x0f}, //saps1=1000
    {LDIC_DISPLAYCTL1_REG, 0x04}, //gon=0,dte=0,D=01 ALL OFF
    {LDIC_DISPLAYCTL1_REG, 0x24}, //GON=1,DTE=0,D=01 DISPLAY OFF, VGL OFF
    {LDIC_DISPLAYCTL1_REG, 0x2C}, //GON=1,DTE=0,D=11 DISPLAY ON