lcd.h

s3c2410中的lcd驱动代码

/*
 * MPC823 and PXA LCD Controller
 *
 * Modeled after video interface by Paolo Scaffardi
 *
 *
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _LCD_H_
#define _LCD_H_

extern char lcd_is_enabled;

extern int lcd_line_length;
extern int lcd_color_fg;
extern int lcd_color_bg;

/*
 * Frame buffer memory information
 */
extern void *lcd_base;		/* Start of framebuffer memory	*/
extern void *lcd_console_address;	/* Start of console buffer	*/

extern short console_col;
extern short console_row;

#if defined CONFIG_MPC823
/*
 * LCD controller stucture for MPC823 CPU
 */
typedef struct vidinfo {
	ushort	vl_col;		/* Number of columns (i.e. 640) */
	ushort	vl_row;		/* Number of rows (i.e. 480) */
	ushort	vl_width;	/* Width of display area in millimeters */
	ushort	vl_height;	/* Height of display area in millimeters */

	/* LCD configuration register */
	u_char	vl_clkp;	/* Clock polarity */
	u_char	vl_oep;		/* Output Enable polarity */
	u_char	vl_hsp;		/* Horizontal Sync polarity */
	u_char	vl_vsp;		/* Vertical Sync polarity */
	u_char	vl_dp;		/* Data polarity */
	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
	u_char	vl_tft;		/* 0 = passive, 1 = TFT */

	/* Horizontal control register. Timing from data sheet */
	ushort	vl_wbl;		/* Wait between lines */

	/* Vertical control register */
	u_char	vl_vpw;		/* Vertical sync pulse width */
	u_char	vl_lcdac;	/* LCD AC timing */
	u_char	vl_wbf;		/* Wait between frames */
} vidinfo_t;

extern vidinfo_t panel_info;

#elif defined CONFIG_S3C24XX         //ADD BY [e-mail]
/*
 * LCD controller stucture for S3C24XX CPU
 */
#include"s3c2440.h"

#define LCD_TM240320LNFWUGWA5

/*
 * S3C LCD info
 */
struct s3cfb_info {
    S3C24X0_LCD S3C24X0_LCD_Info;
    u_long  screen;     /* physical address of frame buffer */
};

typedef struct vidinfo {
    ushort  vl_col;     /* Number of columns (i.e. 640) */
    ushort  vl_row;     /* Number of rows (i.e. 480) */
    ushort  vl_width;   /* Width of display area in millimeters */
    ushort  vl_height;  /* Height of display area in millimeters */

    /* LCD configuration register */
    u_char  vl_clkp;    /* Clock polarity */
    u_char  vl_oep;     /* Output Enable polarity */
    u_char  vl_hsp;     /* Horizontal Sync polarity */
    u_char  vl_vsp;     /* Vertical Sync polarity */
    u_char  vl_dp;      /* Data polarity */
    u_char  vl_bpix;    /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
    u_char  vl_lbw;     /* LCD Bus width, 0 = 4, 1 = 8 */
    u_char  vl_splt;    /* Split display, 0 = single-scan, 1 = dual-scan */
    u_char  vl_clor;    /* Color, 0 = mono, 1 = color */
    u_char  vl_tft;     /* 0 = passive, 1 = TFT */

    /* Horizontal control register. Timing from data sheet */
    ushort  vl_hpw;     /* Horz sync pulse width */
    u_char  vl_blw;     /* Wait before of line */
    u_char  vl_elw;     /* Wait end of line */

    /* Vertical control register. */
    u_char  vl_vpw;     /* Vertical sync pulse width */
    u_char  vl_bfw;     /* Wait before of frame */
    u_char  vl_efw;     /* Wait end of frame */
    //
    struct s3cfb_info s3c;
} vidinfo_t;

extern vidinfo_t panel_info;

//------------------------------------------------------------------------------
//  Define: LCD_TYPE
//
//  Defines the active LCD type from above choices.
//

//  Define: LCD_TYPE_XXX
#define    LCD_TYPE           (3)
#define    LCD_TYPE_TFT16BPP     (12)

#define LCD_RESET_C0IO      0
#define LCD_PCLK_C1IO       1
#define LCD_HCLK_C2IO       2
#define LCD_VCLK_C3IO       3
#define LCD_DEN_C4IO        4
#define LCD_BLUE0_C11IO     11
#define LCD_BLUE1_C12IO     12
#define LCD_BLUE2_C13IO     13
#define LCD_BLUE3_C14IO     14
#define LCD_BLUE4_C15IO     15

#define SPI_CS_D0IO         0
#define SPI_SCL_D1IO        1
#define LCD_GREEN0_D2IO     2
#define LCD_GREEN1_D3IO     3
#define LCD_GREEN2_D4IO     4
#define LCD_GREEN3_D5IO     5
#define LCD_GREEN4_D6IO     6
#define LCD_GREEN5_D7IO     7
#define SPI_SDA_D9IO        9
#define LCD_SD_D10IO       10
#define LCD_RED0_D11IO     11
#define LCD_RED1_D12IO     12
#define LCD_RED2_D13IO     13
#define LCD_RED3_D14IO     14
#define LCD_RED4_D15IO     15


#define LCD_RESET    (1<<0)
#define LCD_SD       (1<<10)

#define SPI_CS     (1<<0)
#define SPI_SCL   (1<<1)
#define SPI_SDA    (1<<9)

#define    LCD_MVAL                (13)
#define    LCD_MVAL_USED           (0)

#if defined(LCD_TD028TTEC1)
//5TODO:LCD MODULE      DEFINE.

#elif defined(LCD_L4F00242T05)
#define LDIC_DISON_CMD      0x29
#define LDIC_DISOFF_CMD     0x28
#define LDIC_GAMSET_CMD     0x26
#define LDIC_SLPIN_CMD      0x10
#define LDIC_SLPOUT_CMD     0x11
#define LDIC_PASET_CMD      0x2B
#define LDIC_CASET_CMD      0x2A
#define LDIC_MADCTL_CMD     0x36
#define LDIC_COLMOD_CMD     0x3A
#define LDIC_RAMWR_CMD      0x2C
#define LDIC_PTLON_CMD      0x12
#define LDIC_PTLAR_CMD      0x30
#define LDIC_NORON_CMD      0x13

#elif defined(LCD_BM240320_4252FTGAN)
//HX8346 register-content interface REGS define
#define LDIC_DISMODECTL_REG         0x01
#define LDIC_SCHI_REG               0x02
#define LDIC_SCLO_REG               0x03
#define LDIC_ECHI_REG               0x04
#define LDIC_ECLO_REG               0x05
#define LDIC_SPHI_REG               0x06
#define LDIC_SPLO_REG               0x07
#define LDIC_EPHI_REG               0x08
#define LDIC_EPLO_REG               0x09
#define LDIC_PSLHI_REG              0x0A
#define LDIC_PSLLO_REG              0x0B
#define LDIC_PELHI_REG              0x0C
#define LDIC_PELLO_REG              0x0D
#define LDIC_TFAHI_REG              0x0E
#define LDIC_TFALO_REG              0x0F
#define LDIC_VSAHI_REG              0x10
#define LDIC_VSALO_REG              0x11
#define LDIC_BFAHI_REG              0x12
#define LDIC_BFALO_REG              0x13
#define LDIC_VSPHI_REG              0x14
#define LDIC_VSPLO_REG              0x15
#define LDIC_MEMACCESSCTL_REG       0x16
#define LDIC_RESERVED1_REG          0x17
#define LDIC_GATESCANCTL_REG        0x18
#define LDIC_OSCCTL1_REG            0x19
#define LDIC_OSCCTL2_REG            0x1A
#define LDIC_PWRCTL1_REG            0x1B
#define LDIC_PWRCTL2_REG            0x1C
#define LDIC_PWRCTL3_REG            0x1D
#define LDIC_PWRCTL4_REG            0x1E
#define LDIC_PWRCTL5_REG            0x1F
#define LDIC_PWRCTL6_REG            0x20
#define LDIC_PWRCTL7_REG            0x21
#define LDIC_SRAMWRITECTL_REG       0x22
#define LDIC_CYCLECTL1_REG          0x23
#define LDIC_CYCLECTL2_REG          0x24
#define LDIC_CYCLECTL3_REG          0x25
#define LDIC_DISPLAYCTL1_REG        0x26
#define LDIC_DISPLAYCTL2_REG        0x27
#define LDIC_DISPLAYCTL3_REG        0x28
#define LDIC_DISPLAYCTL4_REG        0x29
#define LDIC_DISPLAYCTL5_REG        0x2A
#define LDIC_RESERVED2_REG          0x2B
#define LDIC_DISPLAYCTL6_REG        0x2C
#define LDIC_DISPLAYCTL7_REG        0x2D
#define LDIC_RESERVED3_REG          0x2E
#define LDIC_DISPLAYCTL8_REG        0x2F
#define LDIC_DISPLAYCLT9_REG        0x30
#define LDIC_RESERVED4_REG          0x31
#define LDIC_RESERVED5_REG          0x32
#define LDIC_RESERVED6_REG          0x33
#define LDIC_RESERVED7_REG          0x34
#define LDIC_RESERVED8_REG          0x35
#define LDIC_RESERVED9_REG          0x36
#define LDIC_DISPLAYCTL16_REG       0x37
#define LDIC_RGBINTERFACECTL1_REG   0x38
#define LDIC_RGBINTERFACECTL2_REG   0x39
#define LDIC_CYCLECTL4_REG          0x3A
#define LDIC_CYCLECTL5_REG          0x3B
#define LDIC_CYCLECTL6_REG          0x3C
#define LDIC_CYCLECTL7_REG          0x3D
#define LDIC_CYCLECTL8_REG          0x3E
#define LDIC_RESERVED11_REG         0x3F
#define LDIC_CYCLECTL9_REG          0x40
#define LDIC_CYCLECTL10_REG         0x41
#define LDIC_BGPCTL_REG             0x42
#define LDIC_VCOMCTL1_REG           0x43
#define LDIC_VCOMCTL2_REG           0x44
#define LDIC_VCOMCTL3_REG           0x45
#define LDIC_R1CTL1_REG             0x46
#define LDIC_R1CTL2_REG             0x47
#define LDIC_R1CTL3_REG             0x48
#define LDIC_R1CTL4_REG             0x49
#define LDIC_R1CTL5_REG             0x4A
#define LDIC_R1CTL6_REG             0x4B
#define LDIC_R1CTL7_REG             0x4C
#define LDIC_R1CTL8_REG             0x4D
#define LDIC_R1CTL9_REG             0x4E
#define LDIC_R1CTL10_REG            0x4F
#define LDIC_R1CTL11_REG            0x50
#define LDIC_R1CTL12_REG            0x51
#define LDIC_RESERVED12_REG         0x52         
#define LDIC_RESERVED13_REG         0x53
#define LDIC_RESERVED14_REG         0x54
#define LDIC_INTERNALUSE1_REG       0x55
#define LDIC_INTERNALUSE2_REG       0x56
#define LDIC_INTERNALUSE3_REG       0x57
#define LDIC_INTERNALUSE4_REG       0x58
#define LDIC_INTERNALUSE5_REG       0x59
#define LDIC_INTERNALUSE6_REG       0x5A
#define LDIC_INTERNALUSE7_REG       0x5B
#define LDIC_INTERNALUSE8_REG       0x5C
#define LDIC_INTERNALUSE9_REG       0x5D
#define LDIC_INTERNALUSE10_REG      0x5E
#define LDIC_INTERNALUSE11_REG      0x5F
#define LDIC_INTERNALUSE12_REG      0x60
#define LDIC_INTERNALUSE13_REG      0x61
#define LDIC_INTERNALUSE14_REG      0x62
#define LDIC_INTERNALUSE15_REG      0x63
#define LDIC_INTERNALUSE16_REG      0x64
#define LDIC_INTERNALUSE17_REG      0x65
#define LDIC_INTERNALUSE18_REG      0x66
#define LDIC_DRIVERID_REG           0x67
#define LDIC_INTERNALUSE20_REG      0x68
#define LDIC_INTERNALUSE21_REG      0x69
#define LDIC_INTERNALUSE22_REG      0x6A
#define LDIC_INTERNALUSE23_REG      0x6B
#define LDIC_INTERNALUSE24_REG      0x6C
#define LDIC_INTERNALUSE25_REG      0x6D
#define LDIC_RESERVED15_REG         0x6E
#define LDIC_RESERVED16_REG         0x6F
#define LDIC_INTERNALUSE28_REG      0x70
#define LDIC_RESERVED17_REG         0x71
#define LDIC_INTERNALUSE30_REG      0x72
#define LDIC_INTERNALUSE31_REG      0x73
#define LDIC_INTERNALUSE32_REG      0x74
#define LDIC_INTERNALUSE33_REG      0x75
#define LDIC_INTERNALUSE34_REG      0x76
#define LDIC_INTERNALUSE35_REG      0x77
#define LDIC_INTERNALUSE36_REG      0x78
#define LDIC_INTERNALUSE37_REG      0x79
#define LDIC_INTERNALUSE38_REG      0x7A
#define LDIC_INTERNALUSE39_REG      0x7B
#define LDIC_INTERNALUSE40_REG      0x7C
#define LDIC_INTERNALUSE41_REG      0x7D
#define LDIC_INTERNALUSE42_REG      0x7E
#define LDIC_INTERNALUSE43_REG      0x7F
#define LDIC_INTERNALUSE44_REG      0x80
#define LDIC_INTERNALUSE45_REG      0x81
#define LDIC_INTERNALUSE46_REG      0x82
#define LDIC_INTERNALUSE47_REG      0x83
#define LDIC_INTERNALUSE48_REG      0x84

//HX8346 SPI Interfase start byte define.Makeup as following(MSB):
// 01110 + ID + RS + RW
#define LDIC_STARTBYTE_IDBITS   0x1C
#define LDIC_STARTBYTE_IDXWRITE     ((LDIC_STARTBYTE_IDBITS << 2) | (0 << 1) | 0)
#define LDIC_STARTBYTE_STATUSREAD   ((LDIC_STARTBYTE_IDBITS << 2) | (0 << 1) | 1) 
#define LDIC_STARTBYTE_CMDWRITE     ((LDIC_STARTBYTE_IDBITS << 2) | (1 << 1) | 0)
#define LDIC_STARTBYTE_CMDREAD      ((LDIC_STARTBYTE_IDBITS << 2) | (1 << 1) | 1)
#elif defined(LCD_ST7787)
//5TODO:LCD MODULE DEFINE.
#define LDIC_SWRESET_REG            0x01
#define LDIC_RDDID_REG              0x04
#define LDIC_RDDST_REG              0x09
#define LDIC_RDDPM_REG              0x0A
#define LDIC_RDDMADCTL_REG          0x0B
#define LDIC_RDDCOLMOD_REG          0x0C
#define LDIC_RDDIM_REG              0x0D
#define LDIC_RDDSM_REG              0x0E
#define LDIC_RDDSDR_REG             0x0F
#define LDIC_SLPIN_REG              0x10
#define LDIC_SLPOUT_REG             0x11
#define LDIC_PTLON_REG              0x12
#define LDIC_NORON_REG              0x13
#define LDIC_INVOFF_REG             0x20
#define LDIC_INVON_REG              0x21
#define LDIC_GAMSET_REG             0x26
#define LDIC_DISPOFF_REG            0x28
#define LDIC_DISPON_REG             0x29
#define LDIC_CASET_REG              0x2A
#define LDIC_RASET_REG              0x2B
#define LDIC_RAMWR_REG              0x2C
#define LDIC_RGBSET_REG             0x2D   
#define LDIC_RAMHD_REG              0x2E
#define LDIC_PTLAR_REG              0x30
#define LDIC_SCRLAR_REG             0x33
#define LDIC_TEOFF_REG              0x34
#define LDIC_TEON_REG               0x35
#define LDIC_MADCTL_REG             0x36
#define LDIC_VSSCSAD_REG            0x37
#define LDIC_IDMOFF_REG             0x38
#define LDIC_IDMON_REG              0x39