ledtest.h

s3c2410在WINCE下。用EVC编写下的控制LED的代码

#if !defined(AFX_LEDTEST_H__E1B3014D_49B6_470D_A1CA_480A2829D342__INCLUDED_)
#define AFX_LEDTEST_H__E1B3014D_49B6_470D_A1CA_480A2829D342__INCLUDED_

#if _MSC_VER > 1000
#pragma once
#endif // _MSC_VER > 1000

#include "resource.h"

typedef unsigned long          XLLP_UINT32_T,  *P_XLLP_UINT32_T;
typedef volatile XLLP_UINT32_T XLLP_VUINT32_T, *P_XLLP_VUINT32_T;

typedef unsigned long          S3C2410_UINT32_T,  *P_S3C2410_UINT32_T;
typedef volatile S3C2410_UINT32_T S3C2410_VUINT32_T, *P_S3C2410_VUINT32_T;

/**
  GPIO Register Definitions
**/
typedef struct
{
	S3C2410_VUINT32_T rGPFCON;
	S3C2410_VUINT32_T rGPFDAT;
	S3C2410_VUINT32_T rGPFUP;
} S3C2410_GPIO_T, *P_S3C2410_GPIO_T;

typedef struct 
{
	XLLP_VUINT32_T GPLR0;             /* Level Detect Reg. Bank 0 */
    XLLP_VUINT32_T GPLR1;             /* Level Detect Reg. Bank 1 */
    XLLP_VUINT32_T GPLR2;             /* Level Detect Reg. Bank 2 */
    XLLP_VUINT32_T GPDR0;            /* Data Direction Reg. Bank 0 */
    XLLP_VUINT32_T GPDR1;            /* Data Direction Reg. Bank 1 */
    XLLP_VUINT32_T GPDR2;            /* Data Direction Reg. Bank 2 */
    XLLP_VUINT32_T GPSR0;            /* Pin Output Set Reg. Bank 0 */
    XLLP_VUINT32_T GPSR1;            /* Pin Output Set Reg. Bank 1 */
    XLLP_VUINT32_T GPSR2;            /* Pin Output Set Reg. Bank 2 */
    XLLP_VUINT32_T GPCR0;            /* Pin Output Clr Reg. Bank 0 */
    XLLP_VUINT32_T GPCR1;            /* Pin Output Clr Reg. Bank 1 */
    XLLP_VUINT32_T GPCR2;            /* Pin Output Clr Reg. Bank 2 */
    XLLP_VUINT32_T GRER0;   /* Ris. Edge Detect Enable Reg. Bank 0 */
    XLLP_VUINT32_T GRER1;   /* Ris. Edge Detect Enable Reg. Bank 1 */
    XLLP_VUINT32_T GRER2;   /* Ris. Edge Detect Enable Reg. Bank 2 */
    XLLP_VUINT32_T GFER0;   /* Fal. Edge Detect Enable Reg. Bank 0 */
    XLLP_VUINT32_T GFER1;   /* Fal. Edge Detect Enable Reg. Bank 1 */
    XLLP_VUINT32_T GFER2;   /* Fal. Edge Detect Enable Reg. Bank 2 */
    XLLP_VUINT32_T GEDR0;       /* Edge Detect Status Reg. Bank 0 */
    XLLP_VUINT32_T GEDR1;       /* Edge Detect Status Reg. Bank 1 */
    XLLP_VUINT32_T GEDR2;       /* Edge Detect Status Reg. Bank 2 */
    XLLP_VUINT32_T GAFR0_L;  /* Alt. Function Select Reg.[  0:15 ] */
    XLLP_VUINT32_T GAFR0_U;  /* Alt. Function Select Reg.[ 16:31 ] */
    XLLP_VUINT32_T GAFR1_L;  /* Alt. Function Select Reg.[ 32:47 ] */
    XLLP_VUINT32_T GAFR1_U;  /* Alt. Function Select Reg.[ 48:63 ] */
    XLLP_VUINT32_T GAFR2_L;  /* Alt. Function Select Reg.[ 64:79 ] */
    XLLP_VUINT32_T GAFR2_U;  /* Alt. Function Select Reg.[ 80:95 ] */
    XLLP_VUINT32_T GAFR3_L;  /* Alt. Function Select Reg.[ 96:111] */
    XLLP_VUINT32_T GAFR3_U;  /* Alt. Function Select Reg.[112:120] */
    XLLP_VUINT32_T  RESERVED1[35];    /* addr. offset 0x074-0x0fc */
    XLLP_VUINT32_T GPLR3;             /* Level Detect Reg. Bank 3 */
    XLLP_VUINT32_T  RESERVED2[2];      /* addr. offset 0x104-0x108 */
    XLLP_VUINT32_T GPDR3;            /* Data Direction Reg. Bank 3 */
    XLLP_VUINT32_T  RESERVED3[2];      /* addr. offset 0x110-0x114 */
    XLLP_VUINT32_T GPSR3;            /* Pin Output Set Reg. Bank 3 */
    XLLP_VUINT32_T  RESERVED4[2];      /* addr. offset 0x11c-0x120 */
    XLLP_VUINT32_T GPCR3;            /* Pin Output Clr Reg. Bank 3 */
    XLLP_VUINT32_T  RESERVED5[2];      /* addr. offset 0x128-0x12c */
    XLLP_VUINT32_T GRER3;   /* Ris. Edge Detect Enable Reg. Bank 3 */
    XLLP_VUINT32_T  RESERVED6[2];      /* addr. offset 0x134-0x138 */
    XLLP_VUINT32_T GFER3;   /* Fal. Edge Detect Enable Reg. Bank 3 */
    XLLP_VUINT32_T  RESERVED7[2];      /* addr. offset 0x140-0x144 */
    XLLP_VUINT32_T GEDR3;       /* Edge Detect Status Reg. Bank 3 */

} XLLP_GPIO_T, *P_XLLP_GPIO_T;


#endif // !defined(AFX_LEDTEST_H__E1B3014D_49B6_470D_A1CA_480A2829D342__INCLUDED_)