main.s

这是AVR单片机上能跑的嵌入式操作系统salvo

	.module main.c
	.area vector(rom, abs)
	.org 52
	jmp _UART_RX_interrupt
	.org 48
	jmp _SPI_isr
	.area text(rom, con, rel)
	.dbfile E:\PROGRAMS\controller\salvo-M32\main.c
	.dbfunc e TaskA _TaskA fV
;              i -> R20
	.even
_TaskA::
	xcall push_gset1
	.dbline -1
	.dbline 33
; /************************************************************ 
; Copyright (C) 1995-2002 Pumpkin, Inc. and its
; Licensor(s). Freely distributable.
; 
; $Source: C:\\RCS\\d\\salvo\\tut\\tu5\\main.c,v $
; $Author: aek $
; $Revision: 3.7 $
; $Date: 2003-06-13 17:05:12-07 $
; 
; Source for tutorial programs.
; 
; ************************************************************/
; 
; #include "main.h"
; #include "salvo.h"
; #include "app.h"
; #pragma interrupt_handler UART_RX_interrupt:iv_USART_RX
; #pragma interrupt_handler SPI_isr: 13
; 
; #define TASK_A_P      OSTCBP(1) /* task #1        */
; #define TASK_B_P       OSTCBP(2) /*  ""  #2        */
; #define TASK_C_P      OSTCBP(3) /*  ""  #3        */
; #define PRIO_A        10        /* task priorities*/
; #define PRIO_B         10        /*  ""            */
; #define PRIO_C        2         /*  ""            */
; #define BINSEM_UPDATE_PORT_P OSECBP(1) /* binSem #1   */
; 
; _OSLabel(TaskA1)
; _OSLabel(TaskB1)
; _OSLabel(TaskC1)
; 
; void TaskA( void )
; {
	.dbline 35
; 	Uchar i;
; 	Uart_init();
	xcall _Uart_init
	xjmp L7
L6:
	.dbline 38
; 	
;    while(1)
;    	{
	.dbline 39
; 	if(SPI_validFrame)
	lds R24,_bit_flag
	swap R24
	andi R24,#0x0F
	andi R24,1
	breq L9
	.dbline 40
; 		{
	.dbline 41
; 		SPI_validFrame=FALSE;
	lds R24,_bit_flag
	andi R24,239
	sts _bit_flag,R24
	.dbline 42
; 		for(i=0;i<SPI_DatLen+3;i++)
	clr R20
	xjmp L14
L11:
	.dbline 43
	ldi R24,<_SPI_RecvFifo
	ldi R25,>_SPI_RecvFifo
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	ldi R24,<_SPI_TranFifo
	ldi R25,>_SPI_TranFifo
	mov R30,R20
	clr R31
	add R30,R24
	adc R31,R25
	std z+0,R2
L12:
	.dbline 42
	inc R20
L14:
	.dbline 42
	lds R24,_SPI_DatLen
	subi R24,253    ; addi 3
	cp R20,R24
	brlo L11
	.dbline 44
; 			SPI_TranFifo[i]=SPI_RecvFifo[i];
; 		SPI_SendPacket(SPI_DatLen+3,SPI_TranFifo);
	ldi R18,<_SPI_TranFifo
	ldi R19,>_SPI_TranFifo
	lds R16,_SPI_DatLen
	subi R16,253    ; addi 3
	xcall _SPI_SendPacket
	.dbline 46
; 		//Uart_SendPacket(SPI_DatLen+3,SPI_RecvFifo);
; 		}
L9:
L15:
	.dbline 47
	.dbline 47
	ldi R16,<PL_TaskA1
	ldi R17,>PL_TaskA1
	xcall _OSCtxSw
	.dbline 47
	_TaskA1::
	.dbline 47
L16:
	.dbline 47
	.dbline 49
L7:
	.dbline 37
	xjmp L6
X0:
	.dbline -2
L5:
	xcall pop_gset1
	.dbline 0 ; func end
	ret
	.dbsym r i 20 c
	.dbend
	.dbfunc e TaskB _TaskB fV
	.even
_TaskB::
	.dbline -1
	.dbline 53
; 	OS_Yield(TaskA1);
; 	//OS_Delay(30, TaskA1);
;        }
; }
; 
; void TaskB( void )
; {
	xjmp L20
L19:
	.dbline 55
; 	while(1)
; 		{
L22:
	.dbline 58
	.dbline 58
	ldi R16,<PL_TaskB1
	ldi R17,>PL_TaskB1
	xcall _OSCtxSw
	.dbline 58
	_TaskB1::
	.dbline 58
L23:
	.dbline 58
	.dbline 60
L20:
	.dbline 54
	xjmp L19
X1:
	.dbline -2
L18:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e TaskC _TaskC fV
	.even
_TaskC::
	.dbline -1
	.dbline 64
;         //OS_WaitBinSem(BINSEM_UPDATE_PORT_P, OSNO_TIMEOUT, TaskShow1);
; 		
; 		OS_Yield(TaskB1);
; 		//OS_Delay(10, TaskB1);
;     		}
; }
; 
; void TaskC( void )
; {   
	.dbline 65
;     ADC_init();
	xcall _ADC_init
	.dbline 66
L26:
	.dbline 66
; 	for (;;) {
	.dbline 67
; 		PORTD ^= 0x40;
	ldi R24,64
	in R2,0x12
	eor R2,R24
	out 0x12,R2
	.dbline 69
	.dbline 69
	ldi R16,90
	xcall _OSDelay
L30:
	.dbline 69
	.dbline 69
	ldi R16,<PL_TaskC1
	ldi R17,>PL_TaskC1
	xcall _OSCtxSw
	.dbline 69
	_TaskC1::
	.dbline 69
	.dbline 69
	.dbline 69
	.dbline 69
	.dbline 70
	.dbline 66
	.dbline 66
	xjmp L26
X2:
	.dbline -2
L25:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e port_init _port_init fV
	.even
_port_init::
	.dbline -1
	.dbline 73
; 		
;         OS_Delay(90, TaskC1);
;     }
; }
; void port_init(void)
; {
	.dbline 74
;  PORTA = 0x00;
	clr R2
	out 0x1b,R2
	.dbline 75
;  DDRA  = 0xff;
	ldi R24,255
	out 0x1a,R24
	.dbline 76
;  PORTB = 0x00;
	out 0x18,R2
	.dbline 77
;  DDRB  = 0x01;
	ldi R24,1
	out 0x17,R24
	.dbline 78
;  PORTC = 0x00; //m103 output only
	out 0x15,R2
	.dbline 79
;  DDRC  = 0xff;
	ldi R24,255
	out 0x14,R24
	.dbline 80
;  PORTD = 0x00;
	out 0x12,R2
	.dbline 81
;  DDRD  = 0xff;
	out 0x11,R24
	.dbline -2
L33:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e Uart_init _Uart_init fV
	.even
_Uart_init::
	.dbline -1
	.dbline 84
; }
; void Uart_init(void)
; {
	.dbline 85
;  UCSRC = BIT(URSEL) | 0x06;
	ldi R24,134
	out 0x20,R24
	.dbline 86
;  UBRRH = 0x00;
	clr R2
	out 0x20,R2
	.dbline 87
;  UBRRL = 0x33; 
	ldi R24,51
	out 0x9,R24
	.dbline 88
;  UCSRB = ( (1<<RXCIE) |(1<<RXEN) | (1<<TXEN) );
	ldi R24,152
	out 0xa,R24
	.dbline -2
L34:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e main _main fV
	.even
_main::
	sbiw R28,1
	.dbline -1
	.dbline 92
; }
; 
; void main( void )
; {
	.dbline 93
;  	CLI();
	cli
	.dbline 94
; 	port_init();
	xcall _port_init
	.dbline 95
; 	SPI_SlaveInit();
	xcall _SPI_SlaveInit
	.dbline 96
; 	SEI();
	sei
L36:
	.dbline 97
	.dbline 97
	clr R2
	out 0x33,R2
	.dbline 97
	out 0x32,R2
	.dbline 97
	ldi R24,38
	out 0x3c,R24
	.dbline 97
	ldi R24,2
	out 0x39,R24
	.dbline 97
	ldi R24,13
	out 0x33,R24
	.dbline 97
L37:
	.dbline 97
; 	Init();
	.dbline 98
;     OSInit();
	xcall _OSInit
	.dbline 100
;     
;     OSCreateTask(TaskA, TASK_A_P, PRIO_A);
	ldi R24,10
	std y+0,R24
	ldi R18,<_OStcbArea
	ldi R19,>_OStcbArea
	ldi R16,<PL_TaskA
	ldi R17,>PL_TaskA
	xcall _OSCreateTask
	.dbline 101
;     OSCreateTask(TaskB,  TASK_B_P,  PRIO_B);
	ldi R24,10
	std y+0,R24
	ldi R18,<_OStcbArea+7
	ldi R19,>_OStcbArea+7
	ldi R16,<PL_TaskB
	ldi R17,>PL_TaskB
	xcall _OSCreateTask
	.dbline 102
;     OSCreateTask(TaskC, TASK_C_P, PRIO_C);
	ldi R24,2
	std y+0,R24
	ldi R18,<_OStcbArea+14
	ldi R19,>_OStcbArea+14
	ldi R16,<PL_TaskC
	ldi R17,>PL_TaskC
	xcall _OSCreateTask
	.dbline 104
;     
;     OSCreateBinSem(BINSEM_UPDATE_PORT_P, 0);
	clr R18
	ldi R16,<_OSecbArea
	ldi R17,>_OSecbArea
	xcall _OSCreateBinSem
	.dbline 106
;     
;     OSEi(); 
	sei
	.dbline 108
;     
;     for (;;)
L41:
	.dbline 109
	xcall _OSSched
	.dbline 108
	.dbline 108
	xjmp L41
X3:
	.dbline -2
L35:
	adiw R28,1
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e SPI_MasterInit _SPI_MasterInit fV
	.even
_SPI_MasterInit::
	.dbline -1
	.dbline 112
;         OSSched();
; }
; void SPI_MasterInit(void)
; {
	.dbline 113
; 	DDRB=0xB0;
	ldi R24,176
	out 0x17,R24
	.dbline 114
; 	PORTB|=(1<<4);
	sbi 0x18,4
	.dbline 115
; 	SPCR=(1<<SPE)|(1<<MSTR)|(1<<SPR0);
	ldi R24,81
	out 0xd,R24
	.dbline -2
L45:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e SPI_SlaveInit _SPI_SlaveInit fV
	.even
_SPI_SlaveInit::
	.dbline -1
	.dbline 119
; }
; 
; void SPI_SlaveInit(void)
; {
	.dbline 120
; 	DDRB=0x20;
	ldi R24,32
	out 0x17,R24
	.dbline 121
; 	SPCR=(1<<SPIE)|(1<<SPE)|(1<<SPR0);
	ldi R24,193
	out 0xd,R24
	.dbline -2
L46:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e SPI_MasterTransmit _SPI_MasterTransmit fV
	.even
_SPI_MasterTransmit::
	.dbline -1
	.dbline 124
; }
; void SPI_MasterTransmit(void)
; {
	.dbline 125
; 	PORTB&=~(1<<4);
	cbi 0x18,4
	.dbline 126
; 	SPDR=(*Pout_SPI_TranFIfo);
	lds R30,_Pout_SPI_TranFIfo
	lds R31,_Pout_SPI_TranFIfo+1
	ldd R2,z+0
	out 0xf,R2
L48:
	.dbline 127
L49:
	.dbline 127
; 	while(!(SPSR&(1<<SPIF)));
	sbis 0xe,7
	rjmp L48
	.dbline 128
; 	PORTB|=(1<<4);
	sbi 0x18,4
	.dbline -2
L47:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e SPI_SendPacket _SPI_SendPacket fV
;        Pbuffer -> R22,R23
;            len -> R20
	.even
_SPI_SendPacket::
	xcall push_gset2
	movw R22,R18
	mov R20,R16
	.dbline -1
	.dbline 137
; }
; /*Uchar SPI_SlaveReveive(void)
; {
; 	while(!(SPSR&(1<<SPIF)));
; 	return SPDR;
; 	
; }*/
; void SPI_SendPacket(Uchar len, Uchar * Pbuffer)
; {
	.dbline 138
; 	SPI_MasterInit();
	xcall _SPI_MasterInit
	.dbline 139
; 	Pout_SPI_TranFIfo=Pbuffer;
	sts _Pout_SPI_TranFIfo+1,R23
	sts _Pout_SPI_TranFIfo,R22
	xjmp L53
L52:
	.dbline 141
	.dbline 142
	xcall _SPI_MasterTransmit
	.dbline 143
	dec R20
	.dbline 144
	lds R24,_Pout_SPI_TranFIfo
	lds R25,_Pout_SPI_TranFIfo+1
	adiw R24,1
	sts _Pout_SPI_TranFIfo+1,R25
	sts _Pout_SPI_TranFIfo,R24
	.dbline 145
L53:
	.dbline 140
; 	while(len>0)
	clr R2
	cp R2,R20
	brlo L52
	.dbline 146
; 		{
; 		SPI_MasterTransmit();
; 		len--;
; 		Pout_SPI_TranFIfo++;
; 		}
; 	SPI_SlaveInit();
	xcall _SPI_SlaveInit
	.dbline -2
L51:
	xcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym r Pbuffer 22 pc
	.dbsym r len 20 c
	.dbend
	.dbfunc e SPI_isr _SPI_isr fV
	.even
_SPI_isr::
	st -y,R2
	st -y,R24
	st -y,R25
	st -y,R30
	st -y,R31
	in R2,0x3f
	st -y,R2
	.dbline -1
	.dbline 149
; }
; void SPI_isr(void)
; {
	.dbline 150
; 	PORTD=0x80;
	ldi R24,128
	out 0x12,R24
	.dbline 151
; 	if(SPI_validFrame)
	lds R24,_bit_flag
	swap R24
	andi R24,#0x0F
	andi R24,1
	breq L56
	.dbline 152
; 		{return;}
	.dbline 152
	xjmp L55
L56:
	.dbline 153
; 	if(SPI_Status==0x00)
	lds R2,_SPI_Status
	tst R2
	brne L58
	.dbline 154
; 		{
	.dbline 155
; 		SPI_data=SPDR;
	in R2,0xf
	sts _SPI_data,R2
	.dbline 156
; 		if(SPI_data!=0x68)
	mov R24,R2
	cpi R24,104
	breq L60
	.dbline 157
; 			{
	.dbline 158
; 			SPI_Status=0x00;
	clr R2
	sts _SPI_Status,R2
	.dbline 159
; 			}
	xjmp L59
L60:
	.dbline 161
; 		else
; 			{
	.dbline 162
; 			SPI_RecvFifo[0]=0x68;
	ldi R24,104
	sts _SPI_RecvFifo,R24
	.dbline 163
; 			SPI_Status=0x01;
	ldi R24,1
	sts _SPI_Status,R24
	.dbline 164
; 			}
	.dbline 165
; 		}
	xjmp L59
L58:
	.dbline 166
; 	else if(SPI_Status==0x01)
	lds R24,_SPI_Status
	cpi R24,1
	brne L62
	.dbline 167
; 		{
	.dbline 168
; 		SPI_DatLen=SPDR;
	in R2,0xf
	sts _SPI_DatLen,R2
	.dbline 169
; 		SPI_RecvFifo[1]=SPI_DatLen;
	sts _SPI_RecvFifo+1,R2
	.dbline 170
; 		SPI_Status=0x02;
	ldi R24,2
	sts _SPI_Status,R24
	.dbline 171
; 		}
	xjmp L63
L62:
	.dbline 172
; 	else if(SPI_Status==0x02)
	lds R24,_SPI_Status
	cpi R24,2
	brne L65
	.dbline 173
; 		{
	.dbline 174
; 		SPI_RecvFifo[SPI_DatConter+2]=SPDR;
	ldi R24,<_SPI_RecvFifo+2
	ldi R25,>_SPI_RecvFifo+2
	lds R30,_SPI_DatConter
	clr R31
	add R30,R24
	adc R31,R25