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SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_16_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_16_BIT_SIGNAL_4;
when "0010100" => SELECTED_SIGNAL_4 <= SIGNAL_16_BIT_4_4;
SELECTED_SIGNAL_SAMPLE_CLK_4 <= SIGNAL_16_BIT_SAMPLE_CLK_4_4;
SELECTED_CAPTURED_SIGNAL_4 <= CAPTURED_16_BIT_SIGNAL_4;
SELECTED_STATE_4 <= STATE_16_BIT_SIGNAL_4;
-- Add signals as necessary (up to 127 signals)
when others => SELECTED_SIGNAL_4 <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_4 <= '0';
SELECTED_CAPTURED_SIGNAL_4 <= (others => '0');
SELECTED_STATE_4 <= "00";
end case;
end if;
end process;
-- Input multiplexer, trigger signals
INPUT_MUX_TRIGGER_001: process(ASYNC_RESET, CLK, REG248)
begin
if(ASYNC_RESET = '1') then
SELECTED_TRIGGER <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= '0';
TRIGGER_THRESHOLD <= (others => '0');
elsif rising_edge(CLK) then
-- Select one among the different 8-bit signals to trigger on
case REG248(5 downto 0) is
when "000001" => SELECTED_TRIGGER(0) <= TRIGGER_1_BIT_1;
SELECTED_TRIGGER(15 downto 1) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_1_BIT_SAMPLE_CLK_1;
TRIGGER_THRESHOLD(0) <= REG249(0);
TRIGGER_THRESHOLD(15 downto 1) <= (others => '0');
THRESHOLD_SIZE <= ONE_BIT_THRESHOLD;
when "000010" => SELECTED_TRIGGER(0) <= TRIGGER_1_BIT_2;
SELECTED_TRIGGER(15 downto 1) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_1_BIT_SAMPLE_CLK_2;
TRIGGER_THRESHOLD(0) <= REG249(0);
TRIGGER_THRESHOLD(15 downto 1) <= (others => '0');
THRESHOLD_SIZE <= ONE_BIT_THRESHOLD;
when "000011" => SELECTED_TRIGGER(0) <= TRIGGER_1_BIT_3;
SELECTED_TRIGGER(15 downto 1) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_1_BIT_SAMPLE_CLK_3;
TRIGGER_THRESHOLD(0) <= REG249(0);
TRIGGER_THRESHOLD(15 downto 1) <= (others => '0');
THRESHOLD_SIZE <= ONE_BIT_THRESHOLD;
when "000100" => SELECTED_TRIGGER(0) <= TRIGGER_1_BIT_4;
SELECTED_TRIGGER(15 downto 1) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_1_BIT_SAMPLE_CLK_4;
TRIGGER_THRESHOLD(0) <= REG249(0);
TRIGGER_THRESHOLD(15 downto 1) <= (others => '0');
THRESHOLD_SIZE <= ONE_BIT_THRESHOLD;
when "000101" => SELECTED_TRIGGER(1 downto 0) <= TRIGGER_2_BIT_1;
SELECTED_TRIGGER(15 downto 2) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_2_BIT_SAMPLE_CLK_1;
TRIGGER_THRESHOLD(1 downto 0) <= REG249(1 downto 0);
TRIGGER_THRESHOLD(15 downto 2) <= (others => '0');
THRESHOLD_SIZE <= TWO_BIT_THRESHOLD;
when "000110" => SELECTED_TRIGGER(1 downto 0) <= TRIGGER_2_BIT_2;
SELECTED_TRIGGER(15 downto 2) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_2_BIT_SAMPLE_CLK_2;
TRIGGER_THRESHOLD(1 downto 0) <= REG249(1 downto 0);
TRIGGER_THRESHOLD(15 downto 2) <= (others => '0');
THRESHOLD_SIZE <= TWO_BIT_THRESHOLD;
when "000111" => SELECTED_TRIGGER(1 downto 0) <= TRIGGER_2_BIT_3;
SELECTED_TRIGGER(15 downto 2) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_2_BIT_SAMPLE_CLK_3;
TRIGGER_THRESHOLD(1 downto 0) <= REG249(1 downto 0);
TRIGGER_THRESHOLD(15 downto 2) <= (others => '0');
THRESHOLD_SIZE <= TWO_BIT_THRESHOLD;
when "001000" => SELECTED_TRIGGER(1 downto 0) <= TRIGGER_2_BIT_4;
SELECTED_TRIGGER(15 downto 2) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_2_BIT_SAMPLE_CLK_4;
TRIGGER_THRESHOLD(1 downto 0) <= REG249(1 downto 0);
TRIGGER_THRESHOLD(15 downto 2) <= (others => '0');
THRESHOLD_SIZE <= TWO_BIT_THRESHOLD;
when "001001" => SELECTED_TRIGGER(3 downto 0) <= TRIGGER_4_BIT_1;
SELECTED_TRIGGER(15 downto 4) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_4_BIT_SAMPLE_CLK_1;
TRIGGER_THRESHOLD(3 downto 0) <= REG249(3 downto 0);
TRIGGER_THRESHOLD(15 downto 4) <= (others => '0');
THRESHOLD_SIZE <= FOUR_BIT_THRESHOLD;
when "001010" => SELECTED_TRIGGER(3 downto 0) <= TRIGGER_4_BIT_2;
SELECTED_TRIGGER(15 downto 4) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_4_BIT_SAMPLE_CLK_2;
TRIGGER_THRESHOLD(3 downto 0) <= REG249(3 downto 0);
TRIGGER_THRESHOLD(15 downto 4) <= (others => '0');
THRESHOLD_SIZE <= FOUR_BIT_THRESHOLD;
when "001011" => SELECTED_TRIGGER(3 downto 0) <= TRIGGER_4_BIT_3;
SELECTED_TRIGGER(15 downto 4) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_4_BIT_SAMPLE_CLK_3;
TRIGGER_THRESHOLD(3 downto 0) <= REG249(3 downto 0);
TRIGGER_THRESHOLD(15 downto 4) <= (others => '0');
THRESHOLD_SIZE <= FOUR_BIT_THRESHOLD;
when "001100" => SELECTED_TRIGGER(3 downto 0) <= TRIGGER_4_BIT_4;
SELECTED_TRIGGER(15 downto 4) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_4_BIT_SAMPLE_CLK_4;
TRIGGER_THRESHOLD(3 downto 0) <= REG249(3 downto 0);
TRIGGER_THRESHOLD(15 downto 4) <= (others => '0');
THRESHOLD_SIZE <= FOUR_BIT_THRESHOLD;
when "001101" => SELECTED_TRIGGER(7 downto 0) <= TRIGGER_8_BIT_1;
SELECTED_TRIGGER(15 downto 8) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_8_BIT_SAMPLE_CLK_1;
TRIGGER_THRESHOLD(7 downto 0) <= REG249;
TRIGGER_THRESHOLD(15 downto 8) <= (others => '0');
THRESHOLD_SIZE <= EIGHT_BIT_THRESHOLD;
when "001110" => SELECTED_TRIGGER(7 downto 0) <= TRIGGER_8_BIT_2;
SELECTED_TRIGGER(15 downto 8) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_8_BIT_SAMPLE_CLK_2;
TRIGGER_THRESHOLD(7 downto 0) <= REG249;
TRIGGER_THRESHOLD(15 downto 8) <= (others => '0');
THRESHOLD_SIZE <= EIGHT_BIT_THRESHOLD;
when "001111" => SELECTED_TRIGGER(7 downto 0) <= TRIGGER_8_BIT_3;
SELECTED_TRIGGER(15 downto 8) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_8_BIT_SAMPLE_CLK_3;
TRIGGER_THRESHOLD(7 downto 0) <= REG249;
TRIGGER_THRESHOLD(15 downto 8) <= (others => '0');
THRESHOLD_SIZE <= EIGHT_BIT_THRESHOLD;
when "010000" => SELECTED_TRIGGER(7 downto 0) <= TRIGGER_8_BIT_4;
SELECTED_TRIGGER(15 downto 8) <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_8_BIT_SAMPLE_CLK_4;
TRIGGER_THRESHOLD(7 downto 0) <= REG249;
TRIGGER_THRESHOLD(15 downto 8) <= (others => '0');
THRESHOLD_SIZE <= EIGHT_BIT_THRESHOLD;
when "010001" => SELECTED_TRIGGER <= TRIGGER_16_BIT_1;
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_16_BIT_SAMPLE_CLK_1;
TRIGGER_THRESHOLD(15 downto 8) <= REG249;
TRIGGER_THRESHOLD(7 downto 0) <= (others => '0');
THRESHOLD_SIZE <= SIXTEEN_BIT_THRESHOLD;
when "010010" => SELECTED_TRIGGER <= TRIGGER_16_BIT_2;
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_16_BIT_SAMPLE_CLK_2;
TRIGGER_THRESHOLD(15 downto 8) <= REG249;
TRIGGER_THRESHOLD(7 downto 0) <= (others => '0');
THRESHOLD_SIZE <= SIXTEEN_BIT_THRESHOLD;
when "010011" => SELECTED_TRIGGER <= TRIGGER_16_BIT_3;
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_16_BIT_SAMPLE_CLK_3;
TRIGGER_THRESHOLD(15 downto 8) <= REG249;
TRIGGER_THRESHOLD(7 downto 0) <= (others => '0');
THRESHOLD_SIZE <= SIXTEEN_BIT_THRESHOLD;
when "010100" => SELECTED_TRIGGER <= TRIGGER_16_BIT_4;
SELECTED_TRIGGER_SAMPLE_CLK <= TRIGGER_16_BIT_SAMPLE_CLK_4;
TRIGGER_THRESHOLD(15 downto 8) <= REG249;
TRIGGER_THRESHOLD(7 downto 0) <= (others => '0');
THRESHOLD_SIZE <= SIXTEEN_BIT_THRESHOLD;
-- Add signals as necessary (up to 127 signals)
when others => SELECTED_TRIGGER <= (others => '0');
SELECTED_TRIGGER_SAMPLE_CLK <= '0';
TRIGGER_THRESHOLD <= (others => '0');
end case;
end if;
end process;
TRIGGER_SIGNAL_MSb <= '0' when SIGNED_REPRESENTATION_U_SIGNED_N = '0' else
SELECTED_TRIGGER(0) when (THRESHOLD_SIZE = ONE_BIT_THRESHOLD) else
SELECTED_TRIGGER(1) when (THRESHOLD_SIZE = TWO_BIT_THRESHOLD) else
SELECTED_TRIGGER(3) when (THRESHOLD_SIZE = FOUR_BIT_THRESHOLD) else
SELECTED_TRIGGER(7) when (THRESHOLD_SIZE = EIGHT_BIT_THRESHOLD) else
SELECTED_TRIGGER(15); -- (THRESHOLD_SIZE = SIXTEEN_BIT_THRESHOLD)
TRIGGER_THRESHOLD_MSb_001: process(ASYNC_RESET, CLK)
begin
if(ASYNC_RESET = '1') then
TRIGGER_THRESHOLD_MSb <= '0';
elsif rising_edge(CLK) then
if (SIGNED_REPRESENTATION_U_SIGNED_N = '0') then
TRIGGER_THRESHOLD_MSb <= '0';
else
case THRESHOLD_SIZE is
when ONE_BIT_THRESHOLD => TRIGGER_THRESHOLD_MSb <= TRIGGER_THRESHOLD(0);
when TWO_BIT_THRESHOLD => TRIGGER_THRESHOLD_MSb <= TRIGGER_THRESHOLD(1);
when FOUR_BIT_THRESHOLD => TRIGGER_THRESHOLD_MSb <= TRIGGER_THRESHOLD(3);
when EIGHT_BIT_THRESHOLD => TRIGGER_THRESHOLD_MSb <= TRIGGER_THRESHOLD(7);
when others => TRIGGER_THRESHOLD_MSb <= TRIGGER_THRESHOLD(15);
end case;
end if;
end if;
end process;
RESAMPLE_001: process(ASYNC_RESET, CLK, TRIGGER_REARM_TOGGLE, FORCE_TRIGGER_TOGGLE,
START_CAPTURE_TOGGLE, REG250_READ)
begin
if(ASYNC_RESET = '1') then
TRIGGER_REARM_TOGGLE_D <= '0';
TRIGGER_REARM_TOGGLE_D2 <= '0';
FORCE_TRIGGER_TOGGLE_D <= '0';
FORCE_TRIGGER_TOGGLE_D2 <= '0';
START_CAPTURE_TOGGLE_D <= '0';
START_CAPTURE_TOGGLE_D2 <= '0';
REG250_READ_D <= '0';
REG250_READ_D2 <= '0';
elsif rising_edge(CLK) then
TRIGGER_REARM_TOGGLE_D <= TRIGGER_REARM_TOGGLE;
TRIGGER_REARM_TOGGLE_D2 <= TRIGGER_REARM_TOGGLE_D;
FORCE_TRIGGER_TOGGLE_D <= FORCE_TRIGGER_TOGGLE;
FORCE_TRIGGER_TOGGLE_D2 <= FORCE_TRIGGER_TOGGLE_D;
START_CAPTURE_TOGGLE_D <= START_CAPTURE_TOGGLE;
START_CAPTURE_TOGGLE_D2 <= START_CAPTURE_TOGGLE_D;
REG250_READ_D <= REG250_READ;
REG250_READ_D2 <= REG250_READ_D;
end if;
end process;
TRIGGER_REARM <= '1' when (TRIGGER_REARM_TOGGLE_D /= TRIGGER_REARM_TOGGLE_D2) else '0';
START_CAPTURE <= '1' when (START_CAPTURE_TOGGLE_D /= START_CAPTURE_TOGGLE_D2) else '0';
NEXT_WORD_PLEASE <= '1' when (REG250_READ_D = '0' and REG250_READ_D2 = '1') else '0';
-- Compare the selected trigger signal with the trigger threshold.
COMPARISON_RESULT_USIGNED <= '1' when (SELECTED_TRIGGER > TRIGGER_THRESHOLD) else '0';
EQUAL <= '1' when (SELECTED_TRIGGER = TRIGGER_THRESHOLD) else '0';
COMPARISON_RESULT_SIGNED <=
COMPARISON_RESULT_USIGNED when TRIGGER_SIGNAL_MSb = TRIGGER_THRESHOLD_MSb else
'1' when (TRIGGER_SIGNAL_MSb = '0') and (TRIGGER_THRESHOLD_MSb = '1') else '0';
COMPARISON_RESULT <= COMPARISON_RESULT_SIGNED when SIGNED_REPRESENTATION_U_SIGNED_N = '1' else
COMPARISON_RESULT_USIGNED;
-- Trigger conditioning
-- Make it fully independent of trace settings / states, as the
-- trigger signal is shared among several traces.
-- Threshold is unsigned.
TRIGGER <= '1' when (FORCE_TRIGGER_TOGGLE_D /= FORCE_TRIGGER_TOGGLE_D2) else
'0' when (SELECTED_TRIGGER_SAMPLE_CLK = '0') else
'1' when (REG248(7) = '1' and (COMPARISON_RESULT = '1' or EQUAL = '1') and
COMPARISON_RESULT_D = '0' and EQUAL_D = '0') else
'1' when (REG248(7) = '0' and (COMPARISON_RESULT = '0' or EQUAL = '1') and
COMPARISON_RESULT_D = '1' and EQUAL_D = '0') else '0';
CONDITIONAL_RESAMPLING_001: process(ASYNC_RESET, CLK, SELECTED_TRIGGER_SAMPLE_CLK,
COMPARISON_RESULT, EQUAL)
begin
if(ASYNC_RESET = '1') then
COMPARISON_RESULT_D <= '0';
EQUAL_D <= '0';
elsif rising_edge(CLK) then
if (SELECTED_TRIGGER_SAMPLE_CLK = '1') then
-- remember last comparison result (to detect rising/falling edge)
COMPARISON_RESULT_D <= COMPARISON_RESULT;
EQUAL_D <= EQUAL;
end if;
end if;
end process;
-- Address 0 - 511 -> Trace 1
-- Address 512 - 1023 -> Trace 2
-- Address 1024 - 1535 -> Trace 3
-- Address 1536 - 2047 -> Trace 4
REG250 <= SELECTED_CAPTURED_SIGNAL_1 when REG238(2 downto 1) = "00" else
SELECTED_CAPTURED_SIGNAL_2 when REG238(2 downto 1) = "01" else
SELECTED_CAPTURED_SIGNAL_3 when REG238(2 downto 1) = "10" else
SELECTED_CAPTURED_SIGNAL_4;
-- Bit 0: 0: No capture in progress
-- 1: At least one trace is capturing
-- Bit 1: 0: Trigger not found
-- 1: Trigger found (reset upon resuming capture)
-- Bit 2: Start capture toggle
-- Bit 3: Trigger re-arm toggle
MONITORING_001: process(ASYNC_RESET, CLK)
begin
if(ASYNC_RESET = '1') then
REG251 <= (others => '0');
elsif rising_edge(CLK) then
if (SELECTED_STATE_1 = "00") and (SELECTED_STATE_2 = "00") and
(SELECTED_STATE_3 = "00") and (SELECTED_STATE_4 = "00") then
REG251(0) <= '0';
else
REG251(0) <= '1';
end if;
if (START_CAPTURE = '1') then
REG251(1) <= '0';
elsif((SELECTED_STATE_1 =⌨️ 快捷键说明
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