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signal FORCE_TRIGGER_TOGGLE_D: std_logic:= '0';
signal FORCE_TRIGGER_TOGGLE_D2: std_logic:= '0';
signal REG250_READ_D: std_logic;
signal REG250_READ_D2: std_logic;
signal START_CAPTURE_TOGGLE_D: std_logic:= '0';
signal START_CAPTURE_TOGGLE_D2: std_logic:= '0';
signal START_CAPTURE: std_logic;
--// Trace 1-4 multiplexed input signals
signal SELECTED_SIGNAL_1: std_logic_vector(15 downto 0);
signal SELECTED_SIGNAL_SAMPLE_CLK_1: std_logic;
signal SELECTED_SIGNAL_2: std_logic_vector(15 downto 0);
signal SELECTED_SIGNAL_SAMPLE_CLK_2: std_logic;
signal SELECTED_SIGNAL_3: std_logic_vector(15 downto 0);
signal SELECTED_SIGNAL_SAMPLE_CLK_3: std_logic;
signal SELECTED_SIGNAL_4: std_logic_vector(15 downto 0);
signal SELECTED_SIGNAL_SAMPLE_CLK_4: std_logic;
--// Selected trigger signal
signal SELECTED_TRIGGER: std_logic_vector(15 downto 0);
signal SELECTED_TRIGGER_SAMPLE_CLK: std_logic;
-- Tigger threshold
signal TRIGGER_THRESHOLD: std_logic_vector(15 downto 0);
-- Captured signals for traces 1-4
signal CAPTURED_1_BIT_SIGNAL_1: std_logic_vector(7 downto 0);
signal CAPTURED_2_BIT_SIGNAL_1: std_logic_vector(7 downto 0);
signal CAPTURED_4_BIT_SIGNAL_1: std_logic_vector(7 downto 0);
signal CAPTURED_8_BIT_SIGNAL_1: std_logic_vector(7 downto 0);
signal CAPTURED_16_BIT_SIGNAL_1: std_logic_vector(7 downto 0);
signal CAPTURED_1_BIT_SIGNAL_2: std_logic_vector(7 downto 0);
signal CAPTURED_2_BIT_SIGNAL_2: std_logic_vector(7 downto 0);
signal CAPTURED_4_BIT_SIGNAL_2: std_logic_vector(7 downto 0);
signal CAPTURED_8_BIT_SIGNAL_2: std_logic_vector(7 downto 0);
signal CAPTURED_16_BIT_SIGNAL_2: std_logic_vector(7 downto 0);
signal CAPTURED_1_BIT_SIGNAL_3: std_logic_vector(7 downto 0);
signal CAPTURED_2_BIT_SIGNAL_3: std_logic_vector(7 downto 0);
signal CAPTURED_4_BIT_SIGNAL_3: std_logic_vector(7 downto 0);
signal CAPTURED_8_BIT_SIGNAL_3: std_logic_vector(7 downto 0);
signal CAPTURED_16_BIT_SIGNAL_3: std_logic_vector(7 downto 0);
signal CAPTURED_1_BIT_SIGNAL_4: std_logic_vector(7 downto 0);
signal CAPTURED_2_BIT_SIGNAL_4: std_logic_vector(7 downto 0);
signal CAPTURED_4_BIT_SIGNAL_4: std_logic_vector(7 downto 0);
signal CAPTURED_8_BIT_SIGNAL_4: std_logic_vector(7 downto 0);
signal CAPTURED_16_BIT_SIGNAL_4: std_logic_vector(7 downto 0);
-- Selected captured signals for traces 1-4
signal SELECTED_CAPTURED_SIGNAL_1: std_logic_vector(7 downto 0);
signal SELECTED_CAPTURED_SIGNAL_2: std_logic_vector(7 downto 0);
signal SELECTED_CAPTURED_SIGNAL_3: std_logic_vector(7 downto 0);
signal SELECTED_CAPTURED_SIGNAL_4: std_logic_vector(7 downto 0);
-- States for traces 1-4
signal STATE_1_BIT_SIGNAL_1: std_logic_vector(1 downto 0);
signal STATE_2_BIT_SIGNAL_1: std_logic_vector(1 downto 0);
signal STATE_4_BIT_SIGNAL_1: std_logic_vector(1 downto 0);
signal STATE_8_BIT_SIGNAL_1: std_logic_vector(1 downto 0);
signal STATE_16_BIT_SIGNAL_1: std_logic_vector(1 downto 0);
signal STATE_1_BIT_SIGNAL_2: std_logic_vector(1 downto 0);
signal STATE_2_BIT_SIGNAL_2: std_logic_vector(1 downto 0);
signal STATE_4_BIT_SIGNAL_2: std_logic_vector(1 downto 0);
signal STATE_8_BIT_SIGNAL_2: std_logic_vector(1 downto 0);
signal STATE_16_BIT_SIGNAL_2: std_logic_vector(1 downto 0);
signal STATE_1_BIT_SIGNAL_3: std_logic_vector(1 downto 0);
signal STATE_2_BIT_SIGNAL_3: std_logic_vector(1 downto 0);
signal STATE_4_BIT_SIGNAL_3: std_logic_vector(1 downto 0);
signal STATE_8_BIT_SIGNAL_3: std_logic_vector(1 downto 0);
signal STATE_16_BIT_SIGNAL_3: std_logic_vector(1 downto 0);
signal STATE_1_BIT_SIGNAL_4: std_logic_vector(1 downto 0);
signal STATE_2_BIT_SIGNAL_4: std_logic_vector(1 downto 0);
signal STATE_4_BIT_SIGNAL_4: std_logic_vector(1 downto 0);
signal STATE_8_BIT_SIGNAL_4: std_logic_vector(1 downto 0);
signal STATE_16_BIT_SIGNAL_4: std_logic_vector(1 downto 0);
-- Seleced states for traces 1-4
signal SELECTED_STATE_1: std_logic_vector(1 downto 0);
signal SELECTED_STATE_2: std_logic_vector(1 downto 0);
signal SELECTED_STATE_3: std_logic_vector(1 downto 0);
signal SELECTED_STATE_4: std_logic_vector(1 downto 0);
-- State Machine Variables
type THRESHOLD_STATETYPE is (ONE_BIT_THRESHOLD, TWO_BIT_THRESHOLD,
FOUR_BIT_THRESHOLD, EIGHT_BIT_THRESHOLD, SIXTEEN_BIT_THRESHOLD);
signal THRESHOLD_SIZE: THRESHOLD_STATETYPE;
-- Trigger signal MSb and trigger threshold MSb
signal TRIGGER_SIGNAL_MSb: std_logic;
signal TRIGGER_THRESHOLD_MSb: std_logic;
signal COMPARISON_RESULT_USIGNED: std_logic;
signal COMPARISON_RESULT_SIGNED: std_logic;
signal COMPARISON_RESULT: std_logic;
signal COMPARISON_RESULT_D: std_logic;
signal EQUAL: std_logic;
signal EQUAL_D: std_logic;
signal WORD_CLK_IN_1: std_logic;
signal WORD_CLK_IN_2: std_logic;
signal WORD_CLK_IN_3: std_logic;
signal WORD_CLK_IN_4: std_logic;
--------------------------------------------------------
-- IMPLEMENTATION
--------------------------------------------------------
begin
--// COMSCOPE SOURCE CODE -----------
ZERO <= '0';
ONE <= '1';
ZERO8 <= (others => '0');
-- Trace 1 input signal multiplexing
INPUT_MUX_TRACE1_001: process(ASYNC_RESET, CLK, REG240)
begin
if(ASYNC_RESET = '1') then
SELECTED_SIGNAL_1 <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= '0';
SELECTED_CAPTURED_SIGNAL_1 <= (others => '0');
SELECTED_STATE_1 <= "00";
elsif rising_edge(CLK) then
case REG240(6 downto 0) is
-- Select one among the different signals to capture for trace 1
when "0000001" => SELECTED_SIGNAL_1(0) <= SIGNAL_1_BIT_1_1;
SELECTED_SIGNAL_1(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_1_BIT_SAMPLE_CLK_1_1;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_1_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_1_BIT_SIGNAL_1;
when "0000010" => SELECTED_SIGNAL_1(0) <= SIGNAL_1_BIT_1_2;
SELECTED_SIGNAL_1(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_1_BIT_SAMPLE_CLK_1_2;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_1_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_1_BIT_SIGNAL_1;
when "0000011" => SELECTED_SIGNAL_1(0) <= SIGNAL_1_BIT_1_3;
SELECTED_SIGNAL_1(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_1_BIT_SAMPLE_CLK_1_3;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_1_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_1_BIT_SIGNAL_1;
when "0000100" => SELECTED_SIGNAL_1(0) <= SIGNAL_1_BIT_1_4;
SELECTED_SIGNAL_1(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_1_BIT_SAMPLE_CLK_1_4;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_1_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_1_BIT_SIGNAL_1;
when "0000101" => SELECTED_SIGNAL_1(1 downto 0) <= SIGNAL_2_BIT_1_1;
SELECTED_SIGNAL_1(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_2_BIT_SAMPLE_CLK_1_1;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_2_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_2_BIT_SIGNAL_1;
when "0000110" => SELECTED_SIGNAL_1(1 downto 0) <= SIGNAL_2_BIT_1_2;
SELECTED_SIGNAL_1(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_2_BIT_SAMPLE_CLK_1_2;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_2_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_2_BIT_SIGNAL_1;
when "0000111" => SELECTED_SIGNAL_1(1 downto 0) <= SIGNAL_2_BIT_1_3;
SELECTED_SIGNAL_1(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_2_BIT_SAMPLE_CLK_1_3;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_2_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_2_BIT_SIGNAL_1;
when "0001000" => SELECTED_SIGNAL_1(1 downto 0) <= SIGNAL_2_BIT_1_4;
SELECTED_SIGNAL_1(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_2_BIT_SAMPLE_CLK_1_4;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_2_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_2_BIT_SIGNAL_1;
when "0001001" => SELECTED_SIGNAL_1(3 downto 0) <= SIGNAL_4_BIT_1_1;
SELECTED_SIGNAL_1(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_4_BIT_SAMPLE_CLK_1_1;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_4_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_4_BIT_SIGNAL_1;
when "0001010" => SELECTED_SIGNAL_1(3 downto 0) <= SIGNAL_4_BIT_1_2;
SELECTED_SIGNAL_1(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_4_BIT_SAMPLE_CLK_1_2;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_4_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_4_BIT_SIGNAL_1;
when "0001011" => SELECTED_SIGNAL_1(3 downto 0) <= SIGNAL_4_BIT_1_3;
SELECTED_SIGNAL_1(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_4_BIT_SAMPLE_CLK_1_3;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_4_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_4_BIT_SIGNAL_1;
when "0001100" => SELECTED_SIGNAL_1(3 downto 0) <= SIGNAL_4_BIT_1_4;
SELECTED_SIGNAL_1(15 downto 4) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_4_BIT_SAMPLE_CLK_1_4;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_4_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_4_BIT_SIGNAL_1;
when "0001101" => SELECTED_SIGNAL_1(7 downto 0) <= SIGNAL_8_BIT_1_1;
SELECTED_SIGNAL_1(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_8_BIT_SAMPLE_CLK_1_1;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_8_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_8_BIT_SIGNAL_1;
when "0001110" => SELECTED_SIGNAL_1(7 downto 0) <= SIGNAL_8_BIT_1_2;
SELECTED_SIGNAL_1(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_8_BIT_SAMPLE_CLK_1_2;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_8_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_8_BIT_SIGNAL_1;
when "0001111" => SELECTED_SIGNAL_1(7 downto 0) <= SIGNAL_8_BIT_1_3;
SELECTED_SIGNAL_1(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_8_BIT_SAMPLE_CLK_1_3;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_8_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_8_BIT_SIGNAL_1;
when "0010000" => SELECTED_SIGNAL_1(7 downto 0) <= SIGNAL_8_BIT_1_4;
SELECTED_SIGNAL_1(15 downto 8) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_8_BIT_SAMPLE_CLK_1_4;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_8_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_8_BIT_SIGNAL_1;
when "0010001" => SELECTED_SIGNAL_1 <= SIGNAL_16_BIT_1_1;
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_16_BIT_SAMPLE_CLK_1_1;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_16_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_16_BIT_SIGNAL_1;
when "0010010" => SELECTED_SIGNAL_1 <= SIGNAL_16_BIT_1_2;
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_16_BIT_SAMPLE_CLK_1_2;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_16_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_16_BIT_SIGNAL_1;
when "0010011" => SELECTED_SIGNAL_1 <= SIGNAL_16_BIT_1_3;
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_16_BIT_SAMPLE_CLK_1_3;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_16_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_16_BIT_SIGNAL_1;
when "0010100" => SELECTED_SIGNAL_1 <= SIGNAL_16_BIT_1_4;
SELECTED_SIGNAL_SAMPLE_CLK_1 <= SIGNAL_16_BIT_SAMPLE_CLK_1_4;
SELECTED_CAPTURED_SIGNAL_1 <= CAPTURED_16_BIT_SIGNAL_1;
SELECTED_STATE_1 <= STATE_16_BIT_SIGNAL_1;
-- Add signals as necessary (up to 127 signals)
when others => SELECTED_SIGNAL_1 <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_1 <= '0';
SELECTED_CAPTURED_SIGNAL_1 <= (others => '0');
SELECTED_STATE_1 <= "00";
end case;
end if;
end process;
-- Trace 2 input signal multiplexing
INPUT_MUX_TRACE2_001: process(ASYNC_RESET, CLK, REG242)
begin
if(ASYNC_RESET = '1') then
SELECTED_SIGNAL_2 <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= '0';
SELECTED_CAPTURED_SIGNAL_2 <= (others => '0');
SELECTED_STATE_2 <= "00";
elsif rising_edge(CLK) then
case REG242(6 downto 0) is
-- Select one among the different signals to capture for trace 1
when "0000001" => SELECTED_SIGNAL_2(0) <= SIGNAL_1_BIT_2_1;
SELECTED_SIGNAL_2(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_1_BIT_SAMPLE_CLK_2_1;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_1_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_1_BIT_SIGNAL_2;
when "0000010" => SELECTED_SIGNAL_2(0) <= SIGNAL_1_BIT_2_2;
SELECTED_SIGNAL_2(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_1_BIT_SAMPLE_CLK_2_2;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_1_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_1_BIT_SIGNAL_2;
when "0000011" => SELECTED_SIGNAL_2(0) <= SIGNAL_1_BIT_2_3;
SELECTED_SIGNAL_2(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_1_BIT_SAMPLE_CLK_2_3;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_1_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_1_BIT_SIGNAL_2;
when "0000100" => SELECTED_SIGNAL_2(0) <= SIGNAL_1_BIT_2_4;
SELECTED_SIGNAL_2(15 downto 1) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_1_BIT_SAMPLE_CLK_2_4;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_1_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_1_BIT_SIGNAL_2;
when "0000101" => SELECTED_SIGNAL_2(1 downto 0) <= SIGNAL_2_BIT_2_1;
SELECTED_SIGNAL_2(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_2_BIT_SAMPLE_CLK_2_1;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_2_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_2_BIT_SIGNAL_2;
when "0000110" => SELECTED_SIGNAL_2(1 downto 0) <= SIGNAL_2_BIT_2_2;
SELECTED_SIGNAL_2(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_2_BIT_SAMPLE_CLK_2_2;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_2_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_2_BIT_SIGNAL_2;
when "0000111" => SELECTED_SIGNAL_2(1 downto 0) <= SIGNAL_2_BIT_2_3;
SELECTED_SIGNAL_2(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_2_BIT_SAMPLE_CLK_2_3;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_2_BIT_SIGNAL_2;
SELECTED_STATE_2 <= STATE_2_BIT_SIGNAL_2;
when "0001000" => SELECTED_SIGNAL_2(1 downto 0) <= SIGNAL_2_BIT_2_4;
SELECTED_SIGNAL_2(15 downto 2) <= (others => '0');
SELECTED_SIGNAL_SAMPLE_CLK_2 <= SIGNAL_2_BIT_SAMPLE_CLK_2_4;
SELECTED_CAPTURED_SIGNAL_2 <= CAPTURED_2_BIT_SIGNAL_2;
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