📄 syslib.c
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/* sysLib.c - Embedded Planet RPX board system-dependent library */
/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 2001-2004 Embedded Planet, LLC. */
#include "copyright_wrs.h"
/*
modification history
--------------------
02b,11Nov03,gad added EPCFG structure that contains board information
02a,06Jul03,gad first release for VxWorks 5.5
01a,19apr96,tpr written.
*/
/*
DESCRIPTION
This library provides board-specific routines. The chip drivers included are:
ppc860Timer.c - PowerPC/860 Timer library
sysMotCpmEnd.c - configuration module for the motCpmEnd driver
motFecEndEP.c - configuration module for the motFecEnd driver
sysLed.c - driver for user LEDs
INCLUDE FILES: sysLib.h
SEE ALSO:
.pG "Configuration"
*/
/* includes */
#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "stdio.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/vxPpcLib.h"
#include "private/vmLibP.h"
#include "ctype.h"
#include "ipProto.h"
#include "drv/multi/ppc860Siu.h"
#include "rpx.h"
#include "ep8xx.h"
#include <rru852flash.h>
#ifdef INCLUDE_SCC_HDLC
#include "sunSccEnd.h"
#endif
#ifdef INCLUDE_CPM
#include "drv/end/motCpmEnd.h"
#endif
#define IO_SYNC __asm__(" sync")
static char *rpxsig = "RPXsignature=1.0\nNAME=VXWORKS\nSTART=10000\nCOPYTSC=10000:FF840000:D8000\nVERSION=1.0\n";
PHYS_MEM_DESC sysPhysMemDesc [] =
{
{
(void *) LOCAL_MEM_LOCAL_ADRS,
(void *) LOCAL_MEM_LOCAL_ADRS,
LOCAL_MEM_SIZE ,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
},
{
/* NVRAM window. Note if there is no NVRAM, this may be removed to save a PTE */
(void *) NV_RAM_ADRS,
(void *) NV_RAM_ADRS,
NV_RAM_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void *) INTERNAL_MEM_MAP_ADDR,
(void *) INTERNAL_MEM_MAP_ADDR,
INTERNAL_MEM_MAP_SIZE, /* 64 k - Internal Memory Map */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void *) FPGA_CS3_BASE,
(void *) FPGA_CS3_BASE,
FPGA_CS3_SIZE, /* 4 k - Board Control and Status */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void *) FPGA_CS4_BASE,
(void *) FPGA_CS4_BASE,
FPGA_CS4_SIZE, /* 4 k - Board Control and Status */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void *) FPGA_CS5_BASE,
(void *) FPGA_CS5_BASE,
FPGA_CS5_SIZE, /* 4 k - Board Control and Status */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void *) REALTIME_BASE,
(void *) REALTIME_BASE,
REALTIME_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
#ifdef INCLUDE_TFFS
{
(void *) PC_BASE_ADRS_0,
(void *) PC_BASE_ADRS_0,
PC_SIZE_0, /* 1 m - PCMCIA window 0 */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void *) PC_BASE_ADRS_1,
(void *) PC_BASE_ADRS_1,
PC_SIZE_1, /* 32 m - PCMCIA window 1 */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
#endif /* INCLUDE_TFFS */
{
(void *) ROM_BASE_ADRS,
(void *) ROM_BASE_ADRS,
ROM_SIZE, /* Flach memory */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
}
};
int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);
int sysBus = BUS; /* system bus type (VME_BUS, etc) */
int sysCpu = CPU; /* system CPU type (PPC860) */
char *sysBootLine = BOOT_LINE_ADRS; /* address of boot line */
char *sysExcMsg = EXC_MSG_ADRS; /* catastrophic message area */
int sysProcNum; /* processor number of this CPU */
int sysFlags; /* boot flags */
char sysBootHost [BOOT_FIELD_LEN]; /* name of host from which we booted */
char sysBootFile [BOOT_FIELD_LEN]; /* name of file from which we booted */
BOOL sysVmeEnable = FALSE; /* by default no VME */
char *rpxBootParams = NULL; /* address in DPRAM where PlanetCore placed params */
/* Parameters set from the PlanetCore boot parameters */
/* NOTE: Changes in the PlanetCore boot parameter structure may require changes here */
EPCFG epcfg; /* Board configuration data */
LOCAL char sysBoardTypeStr[PARAM_MAX_LEN] = ""; /* BO */
LOCAL char sysBoardRevStr[PARAM_MAX_LEN] = ""; /* BR */
LOCAL char sysCpuTypeStr[PARAM_MAX_LEN] = ""; /* PR */
LOCAL char sysCpuVariantStr[PARAM_MAX_LEN]= ""; /* PV */
LOCAL char sysSerPortStr[PARAM_MAX_LEN] = ""; /* SP */
LOCAL char sysIpAddr[PARAM_MAX_LEN] = ""; /* IP */
LOCAL char sysModelStr[80];
/* forward declarations */
LOCAL void rpxToVxBootParams(char *params);
LOCAL void sysNvRamSetup(void);
LOCAL char *bootParamKeySearch(char *token,char *search_area);
/*
* When using PlanetCore to boot, locally define the nvram routines since the physical size
* of the device is passed via PlanetCore to the BSP rather than being hard coded.
*/
STATUS sysNvRamGet(char *string, int len, int offset);
STATUS sysNvRamSet(char *string, int len, int offset);
#ifdef INCLUDE_SCC_HDLC
/* TODO cpmattach() */
/* This array is used to store the unique Ethernet hardware address */
/* these are filled in with the board specific address, initialized in */
/* sysHwInit from the stored PlanetCore boot loader parameters. */
unsigned char sysScc3EnetAddr [6] = {0x30, 0xa0, 0xc8, 0xfe, 0x00, 0x01};
unsigned char sysScc4EnetAddr [6] = {0x40, 0xa0, 0xc8, 0xfe, 0x00, 0x02};
#endif /* INCLUDE_SCC_HDLC */
#ifdef INCLUDE_CPM
/* This array is used to store the unique Ethernet hardware address */
/* these are filled in with the board specific address, initialized in */
/* sysHwInit from the stored PlanetCore boot loader parameters. */
unsigned char sysCpmEnetAddr [6] = {0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff};
extern STATUS cpmattach();
#endif /* INCLUDE_CPM */
#ifdef INCLUDE_MOT_FEC
/* set the following array to a unique Ethernet hardware address */
unsigned char sysFecEnetAddr [6] = {0xff, 0xee, 0xdd, 0xcc, 0xbb, 0xaa};
STATUS sysFecAttach();
IMPORT STATUS sysFecEnetDisable (UINT32 motCpmaddr);
#endif /* INCLUDE_MOT_FEC */
#ifdef INCLUDE_CPM
void sysCpmEnetDisable (int unit);
void sysCpmEnetIntDisable (int unit);
#endif /* INCLUDE_CPM */
#ifdef INCLUDE_SCC_HDLC
void sysSccEnetDisable (int unit);
void sysSccEnetIntDisable (int unit);
STATUS sysSccAttach(int unit);
#endif /* INCLUDE_SCC_HDLC by Jin*/
extern ULONG immrGet(void);
#include "sysSerial.c"
#include "sysLed.c"
#include "intrCtl/ppc860Intr.c"
#include "ep860Timer.c" /* PPC860 have on chip timers */
#ifdef INCLUDE_SCC_HDLC
#include "sunSccEnd.c" /* configuration module for sunSccEnd by Jin */
#endif /* INCLUDE_SCC_HDLC */
#ifdef INCLUDE_CPM
#include "sysMotCpmEnd.c" /* configuration module for motCpmEnd */
#endif /* INCLUDE_CPM */
#ifdef INCLUDE_MOT_FEC
#include "motFecEndEP.c" /* configuration module for motFecEndEP */
#endif /* INCLUDE_CPM */
#ifdef INCLUDE_SMC_RELOCATE
#include "smc_spi_860.c" /* microcode patch to relocate smc/spi */
#endif /* INCLUDE_SMC_RELOCATE */
/* Replace with parameters normally passed in from PlanetCore */
/*#undef BOOT_WO_PCORE*/
#define BOOT_WO_PCORE
#if defined(BOOT_WO_PCORE)
static unsigned long pCoreParams[] = {
0x0A53423D,0x39363030,0x0A424F3D,0x45503835, /* .SB=9600.BO=EP85 */
0x320A4252,0x3D312E31,0x0A50523D,0x3835320A, /* 2.BR=1.1.PR=852. */
0x50563D54,0x0A4E563D,0x300A0A0A,0x54433D30, /* PV=T.NV=0.TC=0 */
0x0A49503D,0x32302E30,0x2E302E34,0x300A0A54, /* .IP=20.0.0.40.T */
0x49503D32,0x302E302E,0x302E3334,0x0A0A4541, /* IP=10.0.0.175.EA */
0x3D303031,0x30454330,0x35344142,0x460A4431, /* =0010EC004ABF.D1 */
0x3D33320A,0x58543D31,0x30303030,0x3030300A, /* =32.XT=10000000. */
0x53573D31,0x350A5350,0x3D534D43,0x310A0AFF, /* SW=15.SP=SMC1... */
0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, /* ................ */
0xFFFFFFFF
};
static unsigned char rru852Params[0x200];
#endif
/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/
char * sysModel (void)
{
sprintf (sysModelStr, "Embedded Planet %s_%s - MPC%s%s",
sysBoardTypeStr, sysBoardRevStr, sysCpuTypeStr, sysCpuVariantStr);
return (sysModelStr);
}
/******************************************************************************
*
* sysBspRev - return the bsp version with the revision eg 1.0/<x>
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.1/0. BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/
char * sysBspRev (void)
{
return (BSP_VERSION BSP_REV);
}
/*
* change bootline
*/
void change_bootline()
{
char tempbuf[256];
int ix;
int iy;
int iz;
char tarbuf[256];
strncpy(tempbuf,DEFAULT_BOOT_LINE,strlen(DEFAULT_BOOT_LINE)+1);
for(ix = 0; ix < strlen(DEFAULT_BOOT_LINE); ix++)
{
tarbuf[ix] = tempbuf[ix];
if( ('e' == tempbuf[ix]) && ('=' == tempbuf[ix+1]) )
break;
}
ix++;
tarbuf[ix] = tempbuf[ix];
ix++;
iz = ix;
for(iy = 0; iy < 256; iy++)
{
if( ( 0x0a == rpxBootParams[iy]) && ('I' == rpxBootParams[iy+1]) && ( 'P' == rpxBootParams[iy+2]))
break;
}
iy += 4;
for(; iy < 256; iy++)
{
if(0x0a == rpxBootParams[iy])
break;
tarbuf[ix] = rpxBootParams[iy];
ix++;
}
for(; iz < 256; iz++)
{
if(' ' == tempbuf[iz])
break;
}
for(; iz < 256; iz++)
{
tarbuf[ix] = tempbuf[iz];
ix++;
if(0x00 == tempbuf[iz])
break;
}
strncpy(sysBootLine, tarbuf, ix);
}
/******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various feature of the Embedded Planet boards. It sets up
* the control registers, initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/
void sysHwInit (void)
{
EPCFG *cfg = getEpCfg();
unsigned int *ptr;
/* Get the physical location of the IMMR register */
int immrVal = vxImmrGet();
int spllMulFactor = 0;
int spllFreq = 0;
char tempStr[BOOT_LINE_SIZE];
char * bootlineinflash;
cfg->sysBoard = RPX_UNKWN; /* Board type */
cfg->sysBoardRev = RPX_REV_UNKWN; /* Board revision */
cfg->sysCpuType = PROC_UNK; /* Processor type */
cfg->sysCpuVar = PVAR_UNK; /* Processor variant */
cfg->sysXtalFreq = 0; /* Crystal frequency (EXTCLK) */
cfg->sysCpuFreq = 0; /* CPU frequency (EXTCLK*multiplier) */
cfg->sysDecFreq = 0; /* Decrementer frequency (EXTCLK/4) */
cfg->sysBrgClkFreq = 0; /* Baud rate generator clock frequency (BGRCLK) */
cfg->sysConsoleBaud = 9600; /* Baud rate */
cfg->sysMemSize = 0; /* Local RAM memory size */
cfg->sysNvRamSize = 0; /* Local NVRAM size */
cfg->sysSerPort = SMC1; /* Serial port used for monitor port */
#if defined(BOOT_WO_PCORE)
strncpy(rru852Params, (unsigned char *)CONFIG_ADRS_IN_FLASH, 0x200);
if(0x0a != rru852Params[0])
rpxBootParams = (unsigned char *)(pCoreParams);
else
rpxBootParams = (unsigned char *)rru852Params;
/* rpxBootParams = (unsigned char *)(pCoreParams); */ /*yuhm*/
#else
/*
* First we need to retrieve the absolute address of the PlanetCore boot
* parameter structure, that was saved upon entry either by romInit() or
* sysInit() (depending on ROM or RAM boot).
*/
ptr = (unsigned int *)(0x00003000);
rpxBootParams = (unsigned char *)*ptr;
#endif
rpxToVxBootParams(rpxBootParams);
/* Get board information */
cfg->sysBoard = sysBoardType();
cfg->sysBoardRev = sysBoardRevision();
cfg->sysCpuType = sysCpuType();
cfg->sysCpuVar = sysCpuVariant();
cfg->sysSerPort = sysSerPort();
sysCpmReset();
#ifdef INCLUDE_SMC_RELOCATE
doUcodePatch(immrVal);
#endif /* INCLUDE_SMC_RELOCATE */
/*
* Dynamically update the mmu table based on the Planet Core parameter
* for NV Ram size. Also if this is the first boot, set up a default boot
* line for use by vxWorks. This allows the user to update the host IP/name
* which is currently not passed via the DPRAM after Planet Core boots the
* kernel image.
*
* if nvram exists, copy the contents of NVRAM into the sysBootLine (0x4200) location.
* The contents of NVRAM should always be same at this point in code.
*/
/*
sysNvRamSetup();
*/
/*
* If mmu tables are used, this is where we dynamically
* update the entry describing main memory, using sysPhysMemTop().
* We must call sysPhysMemTop () at sysHwInit() time to do
* the memory autosizing based on the information from PlanetCore.
*/
sysPhysMemTop();
/* get clocking parameters */
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