📄 rominit.s
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/* romInit.s - Embedded Planet board ROM initialization module for PlanetCore */
/* Copyright 1984-1998 Wind River Systems, Inc. */
/* Copyright 1996-1998 Motorola, Inc. */
/* Copyright 2001-2004 Embedded Planet, LLC. */
/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.
The entry point, romInit(), is the first code executed on power-up.
It performs the minimal setup needed to call
the generic C routine romStart() with parameter BOOT_COLD.
For Embedded Planet RPX boards, this code is reached after the board is
initially booted with PlanetCore. Thus, very little initialization is required --
all hardware-specific init (such as DRAM timing, clock setup, etc.) is
performed by PlanetCore. Other hardware and device initialization is
performed later in the BSP's sysHwInit() routine.
A second entry point in romInit.s is called romInitWarm(). It is called
by sysToMonitor() in sysLib.c to perform a warm boot.
The warm-start entry point must be written to allow a parameter on
the stack to be passed to romStart().
WARNING:
This code must be Position Independent Code (PIC). This means that it
should not contain any absolute address references. If an absolute address
must be used, it must be relocated by the macro ROM_ADRS(x). This macro
will convert the absolute reference to the appropriate address within
ROM space no matter how the boot code was linked. (For PPC, ROM_ADRS does
not work. You must subtract _romInit and add ROM_TEXT_ADRS to each
absolute address).
This code should not call out to subroutines declared in other modules,
specifically sysLib.o, and sysALib.o. If an outside module is absolutely
necessary, it can be linked into the system by adding the module
to the makefile variable BOOT_EXTRA. If the same module is referenced by
other BSP code, then that module must be added to MACH_EXTRA as well.
Note that some C compilers can generate code with absolute addresses.
Such code should not be called from this module. If absolute addresses
cannot be avoided, then only ROM resident code can be generated from this
module. Compressed and uncompressed bootroms or VxWorks images will not
work if absolute addresses are not processed by the macro ROM_ADRS.
*/
/* defines */
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "cacheLib.h"
#include "asm.h"
#include "config.h"
#include "rpx.h"
#include "regs.h"
#include "drv/multi/ppc860Siu.h"
/* Can't use ROM_ADRS macro with HIADJ and LO macro functions, for PPC */
/* Exported internal functions */
.data
FUNC_EXPORT(_romInit) /* start of system code */
FUNC_EXPORT(romInit) /* start of system code */
FUNC_EXPORT(_romInitWarm) /* start of system code */
FUNC_EXPORT(romInitWarm) /* start of system code */
/* externals */
FUNC_IMPORT(romStart) /* system initialization routine */
.text
.align 2
/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* romInit
* (
* int startType /@ only used by 2nd entry point @/
* )
*/
FUNC_BEGIN(_romInit)
FUNC_LABEL(romInit)
/*
* After exiting the Planet Core boot loader, r3 contains the location in DPRAM where
* the boot loader has saved the boot parameters for use in building the vxWorks boot
* line. We store this at 0x00003000 very briefly until it can be picked up by
* sysHwInit().
*/
/* lis r6, HIADJ(0x00003000)
addi r6, r6, LO(0x00003000)
stw r3, 0(r6)
*/
bl cold /* jump to the cold boot initialization */
nop
FUNC_LABEL(_romInitWarm)
FUNC_LABEL(romInitWarm)
/*
* If this is a warm boot, skip over some initialization.
*/
bl start /* jump to the warm boot initialization */
/* copyright notice appears at beginning of ROM (in TEXT segment) */
.ascii "Copyright 1984-2002 Wind River Systems, Inc."
.align 2
cold:
li r3, BOOT_COLD /* set cold boot as start type */
/* add ljj 20050328 */
/*
* When the PowerPC 860 is powered on, the processor fletch the
* instructions located at the address 0x100. We need to jump
* from the address 0x100 to the Flash space.
*/
lis r4, HIADJ(start) /* load r4 with the address */
addi r4, r4, LO(start) /* of start */
lis r5, HIADJ(romInit) /* load r5 with the address */
addi r5, r5, LO(romInit) /* of romInit() */
lis r6, HIADJ(ROM_TEXT_ADRS) /* load r6 with the address */
addi r6, r6, LO(ROM_TEXT_ADRS) /* of ROM_TEXT_ADRS */
sub r4, r4, r5 /* */
add r4, r4, r6
mtspr LR, r4 /* save destination address*/
/* into LR register */
blr /* jump to flash mem address */
/* add ljj 20050328 end */
/*
* disable external interrupts and Instruction/Data MMU, set
* the exception prefix
*/
start:
mfmsr p0 /* p0 = msr */
INT_MASK(p0, p1) /* mask EE bit */
rlwinm p1, p1, 0, _PPC_MSR_BIT_DR + 1, _PPC_MSR_BIT_IR - 1
rlwinm p1, p1, 0, _PPC_MSR_BIT_IP + 1, _PPC_MSR_BIT_IP - 1
mtmsr p1 /* msr = p1 */
isync /* ISYNC */
/*
* ICTRL - initialize the Intstruction Support Control register
*
*/
lis r5, HIADJ(0x00000007)
addi r5, r5, LO(0x00000007)
mtspr ICTRL, r5
/* disable the instruction/data cache */
LOADPTR (r4, CACHE_CMD_DISABLE)
mtspr IC_CST, r4 /* disable I cache */
mtspr DC_CST, r4 /* disable D cache */
/* unlock the instruction/data cache */
LOADPTR (r4, CACHE_CMD_UNLOCK_ALL) /* load unlock cmd */
mtspr IC_CST, r4 /* unlock all I cache lines */
mtspr DC_CST, r4 /* unlock all D cache lines */
/* invalidate instruction and data caches */
LOADPTR (r4, CACHE_CMD_INVALIDATE) /* load invalidate cmd*/
mtspr IC_CST, r4 /* invalidate all I cache lines */
mtspr DC_CST, r4 /* invalidate all D cache lines */
/*
* initialize the IMMR register before any non-core registers
* modification.
*/
lis r4, HIADJ( INTERNAL_MEM_MAP_ADDR)
addi r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
mtspr IMMR, r4 /* initialize the IMMR register */
mfspr r4, IMMR /* read it back, to be sure */
rlwinm r4, r4, 0, 0, 15 /* only high 16 bits count */
/* SYPCR - turn off the system protection stuff */
lis r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
addi r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
stw r5, SYPCR(0)(r4)
/*
* Map the bank 0 to the flash area - On the ADS board at reset time
* the bank 0 is already used to map the flash.
*/
lis r5, HIADJ( (ROM_BASE_ADRS & BR_BA_MSK) | BR_PS_16 | BR_V)
addi r5, r5, LO((ROM_BASE_ADRS & BR_BA_MSK) | BR_PS_16 | BR_V)
stw r5, BR0(0)(r4)
lis r5, HIADJ( 0xfc000000 | OR_CSNT_SAM | OR_BI | OR_SCY_15_CLK | \
OR_TRLX)
addi r5, r5, LO(0xfc000000 | OR_CSNT_SAM | OR_BI | OR_SCY_15_CLK | \
OR_TRLX)
stw r5, OR0(0)(r4)
/* pre-loading r7 with ' KEYED_REG_UNLOCK_VALUE' (ie, 'unlock it') */
lis r7, HIADJ( KEYED_REG_UNLOCK_VALUE )
addi r7, r7, LO( KEYED_REG_UNLOCK_VALUE )
stw r7, TBSCRK(0)(r4)
stw r7, TBREFF0K(0)(r4)
stw r7, TBREFF1K(0)(r4)
stw r7, TBK(0)(r4)
stw r7, RTCSCK(0)(r4)
stw r7, RTCK(0)(r4)
stw r7, RTSECK(0)(r4)
stw r7, RTCALK(0)(r4)
stw r7, PISCRK(0)(r4)
stw r7, PITCK(0)(r4)
stw r7, SCCRK(0)(r4)
stw r7, PLPRCRK(0)(r4)
stw r7, RSRK(0)(r4)
isync
/* set the SIUMCR */
lis r6, HIADJ( 0x00600080 )
addi r6, r6, LO( 0x00600080 )
stw r6, SIUMCR(0)(r4)
/* TBSCR - initialize the Time Base Status and Control register */
lis r5, HIADJ( 0x0002) /*HIADJ( 0x00c3)*/
addi r5, r5, LO(0x0002)
sth r5, TBSCR(0)(r4)
/* PISCR - */
lis r5, HIADJ( 0x0081)
addi r5, r5, LO(0x0081)
sth r5, PISCR(0)(r4)
/* PLPRCR - */
lis r5, HIADJ( 0x000a4001 )
addi r5, r5, LO( 0x000a4001 )
stw r5, PLPRCR(0)(r4)
/* MPTPR - */
lis r5, HIADJ( 0x2000)
addi r5, r5, LO(0x2000)
sth r6, MPTPR(0)(r4)
/* SCCR - */
lis r5, HIADJ( 0x03820000 )
addi r5, r5, LO( 0x03820000 )
stw r5, SCCR(0)(r4)
/* SDRAM - UPMA init */
/*
* load r6/r7 with the start/end address of the UPM table for an
* SDRAM @ 50MHZ.
*/
lis r6, HIADJ( upmaTableSdram)
addi r6, r6, LO(upmaTableSdram)
lis r7, HIADJ( upmaTableSdramEnd)
addi r7, r7, LO(upmaTableSdramEnd)
/* init UPMA for memory access */
sub r5, r7, r6 /* compute table size */
srawi r5, r5, 2 /* in integer size */
/* convert UpmTable to ROM based addressing */
lis r7, HIADJ(romInit)
addi r7, r7, LO(romInit)
lis r8, HIADJ(ROM_TEXT_ADRS)
addi r8, r8, LO(ROM_TEXT_ADRS)
sub r6, r6, r7 /* subtract romInit base address */
add r6, r6, r8 /* add in ROM_TEXT_ADRS address */
lis r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)
addi r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)
UpmaWriteLoop:
/* write the UPM table in the UPM */
lwz r10, 0(r6) /* get data from table */
stw r10, MDR(0)(r4) /* store the data to MD register */
stw r9, MCR(0)(r4) /* issue command to MCR register */
addi r6, r6, 4 /* next entry in the table */
addi r9, r9, 1 /* next MAD address */
addi r5,r5,-1
cmpwi r5,0
bne UpmaWriteLoop
/* enable SDRAM refresh cycles */
lis r5, HIADJ ( 0xd0904000 )
addi r5, r5,LO ( 0xd0904000 )
stw r5, MAMR(0)(r4)
/* program OR1 and BR1 for 16 Mbytes SDRAM Memory Array */
lis r5, HIADJ ( 0xfE000E00 )
addi r5, r5, LO ( 0xfE000E00 )
stw r5, OR1(0)(r4)
lis r5, HIADJ ((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA \
| BR_V)
addi r5, r5, LO ((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA \
| BR_V)
stw r5, BR1(0)(r4)
/*
lis r5, HIADJ( 0x0001)
addi r5, r5, LO(0x0001)
sth r5, PCDIR(0)(r4)
lis r6, HIADJ( 0x0010)
addi r6, r6, LO(0x0010)
wait200:
lis r5, HIADJ( 0x0001)
addi r5, r5, LO(0x0001)
sth r5, PCDAT(0)(r4)
lis r5, HIADJ( 0x0000)
addi r5, r5, LO(0x0000)
sth r5, PCDAT(0)(r4)
addi r6,r6,-1
cmpwi r6,0
bne wait200
*/
lis r5, HIADJ( 0x88 )
addi r5, r5, LO( 0x88 )
stw r5, MAR(0)(r4)
/*
* Issue precharge command (PRCG) and wait the precharge time (t-rp).
* Run precharge pattern from UPMA location 6.
*/
lis r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_1X | 0x5)
addi r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_1X | 0x5)
stw r5, MCR(0)(r4)
/* run refresh pattern 8 times */
lis r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_8X | 0x30)
addi r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS1 | \
MCR_MCLF_8X | 0x30)
stw r5, MCR(0)(r4)
/*?????????*/
/* lis r5, HIADJ( 0x0001)
addi r5, r5, LO(0x0001)
sth r5, PCDIR(0)(r4)
myloop:
lis r5, HIADJ( 0x0001)
addi r5, r5, LO(0x0001)
sth r5, PCDAT(0)(r4)
lis r5, HIADJ( 0x0000)
addi r5, r5, LO(0x0000)
sth r5, PCDAT(0)(r4)
bl myloop
*/
lis r5, HIADJ( 0x80002106 )
addi r5, r5, LO( 0x80002106 )
stw r5, MCR(0)(r4)
/* program OR3 and BR3 for BCSR */
/* lis r5, HIADJ ( 0xff7f8970 )
addi r5, r5, LO ( 0xff7f8970 )
stw r5, OR3(0)(r4)
lis r5, HIADJ ( 0xfa400001 )
addi r5, r5, LO ( 0xfa400001 )
stw r5, BR3(0)(r4)
*/
/* invalidate entries within both TLBs */
tlbia
/* disable all devices (serial, ethernet, ...) */
/* lis r4, HIADJ(BCSR_RESET_VAL)
lis r5, HIADJ (BCSR)
stw r4, LO(BCSR)(r5) */ /* reset the BCSR register */
/* initialize r2 and r13 according to EABI standard */
/* go to C entry point */
LOADPTR (sp, STACK_ADRS)
/* initialize the stack pointer */
addi sp, sp, -FRAMEBASESZ /* get frame stack */
/*
* calculate C entry point: routine - entry point + ROM base
* routine = romStart
* entry point = romInit = R7
* ROM base = ROM_TEXT_ADRS = R8
* C entry point: romStart - R7 + R8
*/
LOADPTR (r7, romInit)
LOADPTR (r8, ROM_TEXT_ADRS)
LOADPTR (r6, romStart)
sub r6, r6, r7 /* routine - entry point */
add r6, r6, r8 /* + ROM base */
mtlr r6 /* move C entry point to LR */
blr /* jump to the C entry point */
FUNC_END(_romInit)
upmaTableSdram:
/* single read (offset 0x00 in upm ram) */
.long 0x1f07fc04, 0Xeeaefc04, 0x11adfc04, 0xefbbbc00
.long 0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35
/* burst read (offset 0x08 in upm ram) */
.long 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00
.long 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47
.long 0x1ff77c47, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05
.long 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05
/* single write (offset 0x18 in upm ram) */
.long 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47
.long 0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05
/* burst write (offset 0x20 in upm ram) */
.long 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
.long 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0x1FF74C05
.long 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05
.long 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05
/* refresh (offset 0x30 in upm ram) */
.long 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc84, 0xFFFFfc07, 0xFA20017C, 0x0FF74C34
.long 0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4
/* exception (offset 0x3C in upm ram) */
.long 0x7ffffc07, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05
upmaTableSdramEnd:
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