📄 rpx.h
字号:
/* rpx.h - Embedded Planet RPX board header */
/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 2001-2004 Embedded Planet, LLC. */
/*
modification history
--------------------
02a,06Jul03,gad first release for VxWorks 5.5
01a,19apr96,tpr written.
*/
/*
This file contains I/O addresses and related constants for the
RPX Boards.
*/
#ifndef INCrpxh
#define INCrpxh
#include "drv/mem/memDev.h"
#include "drv/intrCtl/ppc860Intr.h"
#define KEYED_REG_UNLOCK_VALUE 0x55CCAA33
#define BUS 0 /* bus-less board */
#define CPU PPC860 /* CPU type */
#define PC_BASE_ADRS_0 0x02000000 /* PCMCIA base address */
#define PC_SIZE_0 0x00100000 /* PCMCIA mapping size */
#define PC_BASE_ADRS_1 0x04000000 /* PCMCIA base address */
#define PC_SIZE_1 0x02000000 /* PCMCIA mapping size */
/* Internal Memory Map base Address */
#define INTERNAL_MEM_MAP_ADDR 0xFA200000
#define INTERNAL_MEM_MAP_SIZE 0x00004000 /* 16K bytes */
/* Board Status and Control Registers - unique to rpx */
#define BCSR_BASE_ADDR 0xFA400000 /* BCSR base address */
#ifdef _ASMLANGUAGE
#define BCSR BCSR_BASE_ADDR /* BCSR address */
#define BCSR0 BCSR_BASE_ADDR /* BCSR address */
#define BCSR1 BCSR_BASE_ADDR + 0x01 /* Register 1 */
#define BCSR2 BCSR_BASE_ADDR + 0x02 /* Register 2 */
#define BCSR3 BCSR_BASE_ADDR + 0x03 /* Register 3 */
#define BCSR4 BCSR_BASE_ADDR + 0x04 /* Register 4 */
#else
#define BCSR ((VINT32 *) (BCSR_BASE_ADDR)) /* BCSR address */
#define BCSR0 ((VINT32 *) (BCSR_BASE_ADDR)) /* Register 0 */
#define BCSR1 ((VINT32 *) (BCSR_BASE_ADDR + 0x01)) /* Register 1 */
#define BCSR2 ((VINT32 *) (BCSR_BASE_ADDR + 0x02)) /* Register 2 */
#define BCSR3 ((VINT32 *) (BCSR_BASE_ADDR + 0x03)) /* Register 3 */
#define BCSR4 ((VINT32 *) (BCSR_BASE_ADDR + 0x04)) /* Register 4 */
#endif /* _ASMLANGUAGE */
/* RPX COMMON - Common board control and status register bit definitions */
/* BCSR0 */
#define COMMON_BCSR_ETHEN 0x80000000 /* Ethernet Enable */
#define COMMON_BCSR_ETHLPBK 0x40000000 /* Ethernet Loopback */
#define COMMON_BCSR_COLTEST 0x20000000 /* Ethernet Collision Test */
#define COMMON_BCSR_FULLDPLX 0x10000000 /* Ethernet Full Duplex */
#define COMMON_BCSR_LED4 0x08000000 /* LED 4 */
#define COMMON_BCSR_LED5 0x04000000 /* LED 5 */
#define COMMON_BCSR_ENNVRAM 0x02000000 /* NVRam Enable */
#define COMMON_BCSR_ENMONXCVR 0x01000000 /* Monitor Transceiver Enable */
/* BCSR1 */
/* BCSR2 */
/* BCSR3 */
#define COMMON_BCSR_D0 0x00000080 /* Switch Setting (MSB) */
#define COMMON_BCSR_D1 0x00000040 /* Switch Setting */
#define COMMON_BCSR_D2 0x00000020 /* Switch Setting */
#define COMMON_BCSR_D3 0x00000010 /* Switch Setting (LSB) */
#define COMMON_BCSR_FLSHRDY 0x00000004 /* Flash Ready */
#define COMMON_BCSR_NVRAMBW 0x00000002 /* NVRam Battery Status */
#define COMMON_BCSR_RTCBW 0x00000001 /* RTC Battery Status */
#define COMMON_BCSR_RESET_VAL 0x3E00F00A
/* EP852 - Board control and status register bit definitions */
/* BCSR registers for EP852*/
/* BCSR0 */
#define EP852_BCSR_ETHEN 0x80000000 /* Ethernet Enable */
#define EP852_BCSR_ETHLPBK 0x40000000 /* Ethernet Loopback */
#define EP852_BCSR_COLTEST 0x20000000 /* Ethernet Collision Test */
#define EP852_BCSR_FULLDPLX 0x10000000 /* Ethernet Full Duplex */
#define EP852_BCSR_LED4 0x08000000 /* LED 4 */
#define EP852_BCSR_LED5 0x04000000 /* LED 5 */
#define EP852_BCSR_ENNVRAM 0x02000000 /* NVRam Enable */
#define EP852_BCSR_ENMONXCVR 0x01000000 /* Monitor Transceiver Enable */
/* BCSR1 */
#define EP852_BCSR_SMCRTS 0x00800000 /* SMC RTS Control */
#define EP852_BCSR_SMCCTS 0x00400000 /* SMC CTS Control */
#define EP852_BCSR_FLASHWP 0x00200000 /* Local FLASH Write Protect Enable */
#define EP852_BCSR_IPA5SEL 0x00100000 /* BVD2/SPKR or INPACK#/DREQ Signal to IPA5 */
#define EP852_BCSR_PCAVCTL0 0x00080000 /* PC Slot A Voltage Control */
#define EP852_BCSR_PCAVCTL1 0x00040000
#define EP852_BCSR_PCAVCTL2 0x00020000
#define EP852_BCSR_PCAVCTL3 0x00010000
/* BCSR2 */
#define EP852_BCSR_MIIRST 0x00008000 /* MII Transceiver Enable */
#define EP852_BCSR_MIIPOWER 0x00004000 /* MII Transceiver Power Up */
#define EP852_BCSR_FIRQ 0x00002000 /* Enable FENET IRQ (PC12) */
#define EP852_BCSR_MIICTL 0x00001000 /* FENET LED Control */
#define EP852_BCSR_FLIG10 0x00000800 /* BCSR FENET LED control */
#define EP852_BCSR_FLIG100 0x00000400
#define EP852_BCSR_FACTH 0x00000200
#define EP852_BCSR_FACTL 0x00000100
/* BCSR3 */
#define EP852_BCSR_D0 0x00000080 /* Switch Setting (MSB) */
#define EP852_BCSR_D1 0x00000040 /* Switch Setting */
#define EP852_BCSR_D2 0x00000020 /* Switch Setting */
#define EP852_BCSR_D3 0x00000010 /* Switch Setting (LSB) */
#define EP852_BCSR_MUXMODE 0x00000008 /* UPM Addressing Mode */
#define EP852_BCSR_FLSHRDY 0x00000004 /* Flash Ready */
#define EP852_BCSR_NVRAMBW 0x00000002 /* NVRam Battery Status */
#define EP852_BCSR_NVRTCIRQ 0x00000001 /* NVRTC IRQ Enable */
/* BCSR4 */
#define EP852_BCSR_SCCSEL 0x80000000 /* SCC3 Routing */
#define EP852_BCSR_SCCDTR 0x40000000 /* SCC3 DTR Signal */
#define EP852_BCSR_SCCDSR 0x20000000 /* SCC3 DSR Signal */
#define EP852_BCSR_SCCENXCVR 0x10000000 /* SCC3 Transceiver Enable */
#define EP852_BCSR_SCCRIIRQ 0x08000000 /* SCC3 Ring Indicator IRQ Enable */
#define EP852_BCSR_SPICS_SEL0 0x02000000 /* SPI CS Select Bit 0 */
#define EP852_BCSR_SPICS_SEL1 0x01000000 /* SPI CS Select Bit 1 */
/* BCSR14 */
#define EP852_BCSR_REV0 0x00008000 /* CPLD Code Revision */
#define EP852_BCSR_REV1 0x00004000
#define EP852_BCSR_REV2 0x00002000
#define EP852_BCSR_REV3 0x00001000
#define EP852_BCSR_REV4 0x00000800
#define EP852_BCSR_REV5 0x00000400
#define EP852_BCSR_REV6 0x00000200
#define EP852_BCSR_REV7 0x00000100
/* BCSR15 */
#define EP852_BCSR_ID0 0x00000080 /* EP852 Board Revision */
#define EP852_BCSR_ID1 0x00000040
#define EP852_BCSR_ID2 0x00000020
#define EP852_BCSR_ID3 0x00000010
#define EP852_BCSR_ID4 0x00000008
#define EP852_BCSR_ID5 0x00000004
#define EP852_BCSR_ID6 0x00000002
#define EP852_BCSR_ID7 0x00000001
#define EP852_BCSR_RESET_VAL 0x3E00000A
/*
* Board Control and Status Register reset value. Used in sysALib.s to place the board in a
* stable state for vxWorks bring up.
*
* NOTE: This value MUST be set by the user to match the type of board in use for proper
* operation
*/
#define BCSR_RESET_VAL EP852_BCSR_RESET_VAL
/* Port Definitions for ENET */
/* EP852 */
#define PA_ENET_RXD_852 0x0010 /* PA11 */
#define PA_ENET_TXD_852 0x0020 /* PA10 */
#define PA_ENET_TCLK_852 0x1000 /* PA3; CLK5 */
#define PA_ENET_RCLK_852 0x2000 /* PA2; CLK6 */
#define PC_ENET_TENA_852 0x0004 /* PC13 */
#define PC_ENET_CLSN_852 0x0100 /* PC7 */
#define PC_ENET_RENA_852 0x0200 /* PC6 */
#define SICR_ENET_MASK_852 0x00ff0000
#define SICR_ENET_CLKRT_852 0x002c0000
/* Port Definitions for SCC serial port */
/* EP852 */
#define PA_SCC_RXD_852 0x0010 /* PA11 */
#define PA_SCC_TXD_852 0x0020 /* PA10 */
#define PC_SCC_CTS_852 0x0100 /* PC7 */
#define PC_SCC_CD_852 0x0200 /* PC6 */
#define PC_SCC_RTS_852 0x0004 /* PC13 */
#define SICR_ENET_MASK_852 0x00ff0000
#define SICR_ENET_CLKRT_852 0x002c0000
#endif /* INCrpxh */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -