📄 71x_init.s
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#******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
#* File Name : 71x_init.s
#* Author : MCD Application Team
#* Date First Issued : 06/23/2004
#* Description : This is the first code executed after RESET.
#* This code used to initialize system stacks
#* and critical peripherals before entering the C code.
#*******************************************************************************
#* History:
#* 01/01/2004 : V1.2
#* 14/07/2004 : V1.3
#******************************************************************************/
# --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
.equ Mode_USR, 0x10
.equ Mode_FIQ, 0x11
.equ Mode_IRQ, 0x12
.equ Mode_SVC, 0x13
.equ Mode_ABT, 0x17
.equ Mode_UNDEF, 0x1B
.equ Mode_SYS, 0x1F /* available on ARM Arch 4 and later */
.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
# --- System memory locations
.equ RAM_Base, 0x20000000
.equ RAM_Limit, 0x20010000
.equ SRAM_Base, 0x60000000
.equ Stack_Base, RAM_Limit
.equ SVC_Stack_Length, 256
.equ IRQ_Stack_Length, 1024
.equ USR_Stack_Length, 1024
.equ FIQ_Stack_Length, 256
.equ ABT_Stack_Length, 256
.equ UNDEF_Stack_Length, 256
.equ SVC_Stack, Stack_Base /* SVC stack */
.equ IRQ_Stack, SVC_Stack-SVC_Stack_Length /* followed by IRQ stack */
.equ USR_Stack, IRQ_Stack-IRQ_Stack_Length /* followed by USR stack */
.equ FIQ_Stack, USR_Stack-USR_Stack_Length /* followed by FIQ stack */
.equ ABT_Stack, FIQ_Stack-FIQ_Stack_Length /* followed by ABT stack */
.equ UNDEF_Stack, ABT_Stack-ABT_Stack_Length /* followed by UNDEF stack */
.equ EIC_Base_addr, 0xFFFFF800/* EIC base address */
.equ ICR_off_addr, 0x00 /* Interrupt Control register offset */
.equ CIPR_off_addr, 0x08 /* Current Interrupt Priority Register offset */
.equ IVR_off_addr, 0x18 /* Interrupt Vector Register offset */
.equ FIR_off_addr, 0x1C /* Fast Interrupt Register offset */
.equ IER_off_addr, 0x20 /* Interrupt Enable Register offset */
.equ IPR_off_addr, 0x40 /* Interrupt Pending Bit Register offset */
.equ SIR0_off_addr, 0x60 /* Source Interrupt Register 0 */
.equ EMI_Base_addr, 0x6C000000/* EMI base address */
.equ BCON0_off_addr, 0x00 /* Bank 0 configuration register offset */
.equ BCON1_off_addr, 0x04 /* Bank 1 configuration register offset */
.equ BCON2_off_addr, 0x08 /* Bank 2 configuration register offset */
.equ BCON3_off_addr, 0x0C /* Bank 3 configuration register offset */
.equ EMI_ENABLE, 0x8000
.equ EMI_SIZE_16, 0x0001
.equ GPIO2_Base_addr, 0xE0005000/* GPIO2 base address */
.equ PC0_off_addr, 0x00 /* Port Configuration Register 0 offset */
.equ PC1_off_addr, 0x04 /* Port Configuration Register 1 offset */
.equ PC2_off_addr, 0x08 /* Port Configuration Register 2 offset */
.equ PD_off_addr, 0x0C /* Port Data Register offset */
.equ CPM_Base_addr, 0xA0000040/* CPM Base Address */
.equ BOOTCR_off_addr, 0x10 /* CPM - Boot Configuration Register */
.equ FLASH_mask, 0x0000 /* to remap FLASH at 0x0 */
.equ RAM_mask, 0x0002 /* to remap RAM at 0x0 */
.equ EXTMEM_mask, 0x0003 /* to remap EXTMEM at 0x0 */
#|----------------------------------------------------------------------------------|
#| - APB Bridge (System Peripheral) |
#|----------------------------------------------------------------------------------|
.equ APB1_base_addr, 0xC0000000 /* APB Bridge1 Base Address */
.equ APB2_base_addr, 0xE0000000 /* APB Bridge2 Base Address */
.equ CKDIS_off_addr, 0x10 /* APB Bridge1 - Clock Disable Register */
.equ SWRES_off_addr, 0x14 /* APB Bridge1 - Software Reset Register */
.equ CKDIS1_config_all, 0x27FB /* To enable/disable clock of all APB1's peripherals */
.equ SWRES1_config_all, 0x27FB /* To reset all APB1's peripherals */
.equ CKDIS2_config_all, 0x7FDD /* To enable/disable clock of all APB2's peripherals */
.equ SWRES2_config_all, 0x7FDD /* To reset all APB2's peripherals */
#*******************************************************************************
#******* -- MACROS -- *******
#*******************************************************************************
#*******************************************************************************
#* Macro Name : EMI_INIT
#* Description : This macro Initialise EMI bank 1.
#* Input : None.
#* Output : None.
#*******************************************************************************
.macro EMI_INIT
LDR r0, =GPIO2_Base_addr /* Configure P2.0 -> 3 in AF_PP mode */
LDR r2, [r0, #PC0_off_addr]
ORR r2, r2,#0x0000000F
STR r2, [r0, #PC0_off_addr]
LDR r2, [r0, #PC1_off_addr]
ORR r2, r2,#0x0000000F
STR r2, [r0, #PC1_off_addr]
LDR r2, [r0, #PC2_off_addr]
ORR r2, r2,#0x0000000F
STR r2, [r0, #PC2_off_addr]
LDR r0, =EMI_Base_addr
LDR r1, =0x18 | EMI_ENABLE | EMI_SIZE_16
STR r1, [r0, #BCON1_off_addr] /* Enable bank 1 16-bit 7 wait state */
.endm
#*******************************************************************************
#* Macro Name : EIC_INIT
#* Description : This macro Initialize the EIC as following :
# - IRQ disabled
# - FIQ disabled
# - IVR contain the load PC opcode (0xF59FF00)
# - Current priority level equal to 0
# - All channels are disabled
# - All channels priority equal to 0
# - All SIR registers contain offset to the related IRQ
# table entry
#* Input : None.
#* Output : None.
#*******************************************************************************
.macro EIC_INIT
LDR r3, =EIC_Base_addr
LDR r4, =0xE59F0000
STR r4, [r3, #IVR_off_addr]/* Write the LDR pc,[pc,#offset] */
/* instruction code in IVR[31:16] */
LDR r2, =32 /* 32 Channel to initialize */
LDR r0, =T0TIMI_Addr /* Read the address of the IRQs */
/* address table */
LDR r1, =0x00000FFF
AND r0,r0,r1
LDR r5, =SIR0_off_addr /* Read SIR0 address */
SUB r4,r0,#8 /* subtract 8 for prefetch */
LDR r1, =0xF7E8 /* add the offset to the 0x00000000 */
/* address(IVR address + 7E8 = 0x00000000) */
/* 0xF7E8 used to complete the */
/* LDR pc,[pc,#offset] opcode */
ADD r1,r4,r1 /* compute the jump offset */
EIC_INI:
MOV r4, r1, LSL #16 /* Left shift the result */
STR r4, [r3, r5] /* Store the result in SIRx register */
ADD r1, r1, #4 /* Next IRQ address */
ADD r5, r5, #4 /* Next SIR */
SUBS r2, r2, #1 /* Decrement the number of SIR registers */
/* to initialize */
BNE EIC_INI /* If more then continue */
.endm
#*******************************************************************************
#* Macro Name : PERIPHERAL_INIT
#* Description : This macro reset all device peripherals.
#* Input : None.
#* Output : None.
#*******************************************************************************
.macro PERIPHERAL_INIT
LDR r1, =APB1_base_addr /* r0= APB1 base address */
LDR r2, =APB2_base_addr /* r0= APB2 base address */
LDR r0, =CKDIS1_config_all
STRH r0, [r1, #CKDIS_off_addr]/* Clock Disabling for all APB1 peripherals */
LDR r0, =CKDIS2_config_all
STRH r0, [r2, #CKDIS_off_addr]/* Clock Disabling for all APB2 peripherals */
LDR r0, =SWRES1_config_all
STRH r0, [r1, #SWRES_off_addr]/* Keep under reset all APB1 peropherals */
LDR r0, =SWRES2_config_all
STRH r0, [r2, #SWRES_off_addr]/* Keep under reset all APB2 peropherals */
MOV r7, #10 /* Wait that the selected macrocells exit from reset */
loop1: SUBS r7, r7, #1
BNE loop1
MOV r0, #0
STRH r0, [r1, #SWRES_off_addr]/* Enable all all APB1 peropherals */
STRH r0, [r2, #SWRES_off_addr]/* Enable all all APB2 peropherals */
STRH r0, [r1, #CKDIS_off_addr]/* Clock Enabling for all APB1 peripherals */
STRH r0, [r2, #CKDIS_off_addr]/* Clock Enabling for all APB2 peripherals */
MOV r7, #10 /* Wait that the selected macrocells exit from reset */
loop2: SUBS r7, r7, #1
BNE loop2
.endm
# define remapping
# If you need to remap memory before entring the main program
# uncomment next ligne
@.equ remapping, 1
# Then define which memory to remap to address 0x00000000
# Uncomment next line if you want to remap RAM
@.equ remap_ram, 1
# Uncomment next line if you want to remap FLASH
@.equ remap_flash, 1
# Uncomment next line if you want to remap the external memory
@.equ remap_ext, 1
.text
ENTRY:
.global Reset_Handler
.extern T0TIMI_Addr
Reset_Handler:
LDR pc, =NextInst
NextInst:
NOP /* Wait for OSC stabilization */
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MSR CPSR_c, #Mode_ABT | F_Bit | I_Bit
LDR SP, =ABT_Stack
MSR CPSR_c, #Mode_UNDEF | F_Bit | I_Bit
LDR SP,= UNDEF_Stack
MSR CPSR_c, #Mode_SVC | F_Bit | I_Bit
LDR SP, =RAM_Limit
# Uncomment next ligne if you need to reset all device pripherals
PERIPHERAL_INIT /* Reset all device peripherals */
# Uncomment next ligne if you need to enable the EMI Bank 1
# EMI_INIT /* Initialize EIM Bank 1 */
#Uncomment next ligne if you need to initialize the EIC
EIC_INIT /* Initialize EIC */
#******************************************************************************
#REMAPPING
#Description : Remapping memory whether RAM,FLASH or External memory
# at Address 0x0 after the application has started executing.
# Remapping is generally done to allow RAM to replace FLASH
# or EXTMEM at 0x0.
# the remapping of RAM allow copying of vector table into RAM
#******************************************************************************
.ifdef remapping
.ifdef remap_flash
MOV r0, #FLASH_mask
.endif
.ifdef remap_ram
MOV r0, #RAM_mask
.endif
.ifdef remap_ext
MOV r0, #EXTMEM_mask
.endif
LDR r1, =CPM_Base_addr
LDRH r2, [r1, #BOOTCR_off_addr]/* Read BOOTCR Register */
BIC r2, r2, #0x03 /* Reset the two LSB bits of BOOTCR */
ORR r2, r2, r0 /* change the two LSB bits of BOOTCR */
STRH r2, [r1, #BOOTCR_off_addr]/* Write BOOTCR Register */
.endif
MSR CPSR_c, #Mode_FIQ | F_Bit | I_Bit/* Change to FIQ mode */
LDR SP, =FIQ_Stack /* Initialize FIQ stack pointer */
MSR CPSR_c, #Mode_IRQ | F_Bit | I_Bit/* Change to IRQ mode */
LDR SP, =IRQ_Stack /* Initialize IRQ stack pointer */
MSR CPSR_c, #Mode_SYS | F_Bit | I_Bit/* Change to System mode */
LDR SP, =USR_Stack /* Initialize USR stack pointer */
#********************************************************
#* Copy and paste RW data/zero initialized data *
#********************************************************
.extern Image_RO_Limit /* End of ROM code (=start of ROM data) */
.extern Image_RW_Base /* Base of RAM to initialise */
.extern Image_ZI_Base /* Base and limit of area */
.extern Image_ZI_Limit /* to zero initialise */
LDR r0, =Image_RO_Limit /* Get pointer to ROM data */
LDR r1, =Image_RW_Base /* and RAM copy */
LDR r3, =Image_ZI_Base /* Zero init base => top of initialised data */
CMP r0, r1 /* Check that they are different */
BEQ F1
F0:
CMP r1, r3 /* Copy init data */
LDRCC r2, [r0], #4 /* --> LDRCC r2, [r0] + ADD r0, r0, #4 */
STRCC r2, [r1], #4 /* --> STRCC r2, [r1] + ADD r1, r1, #4 */
BCC F0
F1:
LDR r1, =Image_ZI_Limit /* Top of zero init segment */
MOV r2, #0
F2:
CMP r3, r1 /* Zero init */
STRCC r2, [r3], #4
BCC F2
MSR CPSR_c, #Mode_SYS /* Enable IRQ and FIQ */
.extern Main
# --- Now branches to a C lib function that copies RO data from their
# load region to their execute region, create the RW and ZI regions
# then jumps to user C main program.
B Main /* Note : use B not BL, because an application will */
/* never return this way */
.ltorg
#******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****
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