vhdloperator.java

一种将c高级语言转化给VHDL的编译器

    } else if (type == fp.circuit.Operation.MUX) {
      int size = getInPorts().size();
      Iterator iter = getInPorts().iterator(); 
      
      VHDLNet in0, in1, s;
      PortTag tag = findInPort("in0");
      
      if (tag == null) {
	throw new SynthesisException("Operator "+getName()
				     +" Mux without in0 input - out "+
				     out+" out net "+net+"\n"+this.toString());
      }

      in0 = (VHDLNet)tag.getNet();
      tag = findInPort("in1");
      in1 = (VHDLNet)tag.getNet();
      tag = findInPort("s");
      s = (VHDLNet)tag.getNet();

      // in0 when s = 0
      csa.addCondition(new Waveform(in0.getVHDLName()), 
		       new Expression(new Eq(s.getVHDLName(), Char.ZERO)));
      // else in1 when s = 1;
      csa.addCondition(new Waveform(in1.getVHDLName()), 
		       new Expression(new Eq(s.getVHDLName(), Char.ONE)));
    } else if (type.getName().equals("aaa_setlt")) {

      VHDLNet in0, in1;
      PortTag tag = findInPort("in0");
      in0 = (VHDLNet)tag.getNet();
      tag = findInPort("in1");
      in1 = (VHDLNet)tag.getNet();

      FunctionCall fc0 = new FunctionCall(new SimpleName("signed"));
      fc0.add(in0.getVHDLName());

      FunctionCall fc1 = new FunctionCall(new SimpleName("signed"));
      fc1.add(in1.getVHDLName());

      csa.addCondition(new Waveform(Char.ONE),
		       new Expression(new Lt(fc0, fc1)));
      csa.addCondition(new Waveform(Char.ZERO), null);

    } else if (type.getName().equals("aaa_setle")) {

      VHDLNet in0, in1;
      PortTag tag = findInPort("in0");
      in0 = (VHDLNet)tag.getNet();
      tag = findInPort("in1");
      in1 = (VHDLNet)tag.getNet();

      FunctionCall fc0 = new FunctionCall(new SimpleName("signed"));
      fc0.add(in0.getVHDLName());

      FunctionCall fc1 = new FunctionCall(new SimpleName("signed"));
      fc1.add(in1.getVHDLName());

      csa.addCondition(new Waveform(Char.ONE),
		       new Expression(new Le(fc0, fc1)));
      csa.addCondition(new Waveform(Char.ZERO), null);

    } else if (type.getName().equals("aaa_setgt")) {

      VHDLNet in0, in1;
      PortTag tag = findInPort("in0");
      in0 = (VHDLNet)tag.getNet();
      tag = findInPort("in1");
      in1 = (VHDLNet)tag.getNet();

      FunctionCall fc0 = new FunctionCall(new SimpleName("signed"));
      fc0.add(in0.getVHDLName());

      FunctionCall fc1 = new FunctionCall(new SimpleName("signed"));
      fc1.add(in1.getVHDLName());

      csa.addCondition(new Waveform(Char.ONE),
		       new Expression(new Gt(fc0, fc1)));
      csa.addCondition(new Waveform(Char.ZERO), null);

    } else if (type.getName().equals("aaa_setge")) {

      VHDLNet in0, in1;
      PortTag tag = findInPort("in0");
      in0 = (VHDLNet)tag.getNet();
      tag = findInPort("in1");
      in1 = (VHDLNet)tag.getNet();

      FunctionCall fc0 = new FunctionCall(new SimpleName("signed"));
      fc0.add(in0.getVHDLName());

      FunctionCall fc1 = new FunctionCall(new SimpleName("signed"));
      fc1.add(in1.getVHDLName());

      csa.addCondition(new Waveform(Char.ONE),
		       new Expression(new Ge(fc0, fc1)));
      csa.addCondition(new Waveform(Char.ZERO), null);

    } else if (type.getName().equals("aaa_seteq")) {

      VHDLNet in0, in1;
      PortTag tag = findInPort("in0");
      in0 = (VHDLNet)tag.getNet();
      tag = findInPort("in1");
      in1 = (VHDLNet)tag.getNet();

      csa.addCondition(new Waveform(Char.ONE),
		       new Expression(new Eq(in0.getVHDLName(),
					     in1.getVHDLName())));
      csa.addCondition(new Waveform(Char.ZERO), null);

    } else if (type.getName().equals("aaa_setne")) {

      VHDLNet in0, in1;
      PortTag tag = findInPort("in0");
      in0 = (VHDLNet)tag.getNet();
      tag = findInPort("in1");
      in1 = (VHDLNet)tag.getNet();

      csa.addCondition(new Waveform(Char.ONE),
		       new Expression(new Ne(in0.getVHDLName(),
					     in1.getVHDLName())));
      csa.addCondition(new Waveform(Char.ZERO), null);

    } else if (type.getName().equals("aaa_cshl")) {
      VHDLNet in0 = (VHDLNet)((PortTag)findInPort("in0")).getNet();
	
      int const_in1 = -1;
      VHDLNet in1 = (VHDLNet)((PortTag)findInPort("in1")).getNet();
      for (Iterator net_iter = in1.getSources().iterator(); 
	   net_iter.hasNext();) {
	PortTag pt = (PortTag) net_iter.next();
	Node pt_parent = pt.getParent();
	if (pt_parent instanceof Constant) {
	  const_in1 = ((Constant)pt_parent).getValueInt();
	}
      }
      
      int width = in0.getWidth();
      /*
       we have width and const_in1
       what if const_in1 = 0  or is < 0?
       -- we can either barf or expect that constant op will have taken
       care of it.

       what if width - const_in1 <= 0 ?
       -- this is covered.
       
       this works, but may need to be more robust ...
      */

      Primary se = null;
      
      if (width > const_in1) {
	SliceName slice = new SliceName(in0.getVHDLName(), 
					width - 1 - const_in1, 0);
	se = new Concat(slice);
      
	String zero_s = "";
	for (int i = 0; i< const_in1; i++) {
	  zero_s += "0";
	}

	BitStringLiteral zero = new BitStringLiteral("B",zero_s);
	((Concat)se).concat(zero);
      } else {
	se = VHDLConstant.genConstant(BigInteger.ZERO, width);
      }
      
      
      csa.addCondition(new Waveform(se), null);

    } else if (type.getName().equals("aaa_cshr")) {
      VHDLNet in0 = (VHDLNet)((PortTag)findInPort("in0")).getNet();
	
      int const_in1 = -1;
      VHDLNet in1 = (VHDLNet)((PortTag)findInPort("in1")).getNet();
      for (Iterator net_iter = in1.getSources().iterator(); 
	   net_iter.hasNext();) {
	PortTag pt = (PortTag) net_iter.next();
	Node pt_parent = pt.getParent();
	if (pt_parent instanceof Constant) {
	  const_in1 = ((Constant)pt_parent).getValueInt();
	}
      }
      
      int width = in0.getWidth();
      /*
       we have width and const_in1
       what if const_in1 = 0  or is < 0?
       -- we can either barf or expect that constant op will have taken
       care of it.

       what if width - const_in1 <= 0 ?
       -- this is covered.
       
       this works, but may need to be more robust ...
      */

      Primary se = null;
      
      if (width > const_in1) {
	SliceName slice = new SliceName(in0.getVHDLName(), 
					width - 1, const_in1);
	String zero_s = "";
	for (int i = 0; i< const_in1; i++) {
	  zero_s += "0";
	}

	BitStringLiteral zero = new BitStringLiteral("B",zero_s);
	
	se = new Concat(zero);
	((Concat)se).concat(slice);
      } else {
	se = VHDLConstant.genConstant(BigInteger.ZERO, width);
      }
      
      
      csa.addCondition(new Waveform(se), null);
      
    } else if (type.getName().equals("aaa_some_libop")) {

      // what library
      // what ports map to what ports
      // outs -> VHDL outs
      // ins -> VHDL ins
      // needs clock ?
      // what is the library name
      // what is the VHDL name
      
    } else {

      /*
      System.out.println("VHDLOperator::build() I do not know how to handle type "+type.getName()+" "+type.getSymbol()+"  ");
      System.exit(-1);
      */

      throw new SynthesisException("VHDLOperator::build() I tried everything else and" + 
			     "I do not know how to handle type "
			     +type.getName()+" "+type.getSymbol()+"\n"
			     +this.toString());
    }
    }
  }
}