vhdlcircuit.java

一种将c高级语言转化给VHDL的编译器

/*
 *
 LA-CC 05-135 Trident 0.7.1

Copyright Notice
Copyright 2006 (c) the Regents of the University of California.

This Software was produced under a U.S. Government contract
(W-7405-ENG-36) by Los Alamos National Laboratory, which is operated
by the University of California for the U.S. Department of Energy. The
U.S. Government is licensed to use, reproduce, and distribute this
Software. Permission is granted to the public to copy and use this
Software without charge, provided that this Notice and any statement
of authorship are reproduced on all copies. Neither the Government nor
the University makes any warranty, express or implied, or assumes any
liability or responsibility for the user of this Software.

 
 */ 
package fp.circuit.vhdl;

import java.util.HashMap;
import java.util.HashSet;
import java.util.Iterator;
import java.util.ListIterator;

import java.math.BigInteger;

import java.io.File;
import java.io.PrintWriter;
import java.io.Writer;

import fp.GlobalOptions;
import fp.util.FileTree;

import fp.circuit.*;
import fp.circuit.dot.DotCircuit;

import fp.hwdesc.Read;
import fp.hwdesc.Write;
import fp.hwdesc.Wait;
import fp.hwdesc.FabIn;
import fp.hwdesc.Run;
import fp.hwdesc.Command;
import fp.hwdesc.ParseTestbench;

// these are spelled out to avoid name clash with
// circuit.Operator and generator.Operator.
import fp.util.vhdl.generator.Architecture;
import fp.util.vhdl.generator.AssertionStatement;
import fp.util.vhdl.generator.Char;
import fp.util.vhdl.generator.Component;
import fp.util.vhdl.generator.Concat;
import fp.util.vhdl.generator.ConditionalSignalAssignment;
import fp.util.vhdl.generator.ConstantItem;
import fp.util.vhdl.generator.Entity;
import fp.util.vhdl.generator.Expression;
import fp.util.vhdl.generator.Eq;
import fp.util.vhdl.generator.FunctionCall;
import fp.util.vhdl.generator.DesignFile;
import fp.util.vhdl.generator.DesignUnit;
import fp.util.vhdl.generator.Div;
import fp.util.vhdl.generator.Instance;
import fp.util.vhdl.generator.LibraryUnit;
import fp.util.vhdl.generator.Literal;
import fp.util.vhdl.generator.Mult;
import fp.util.vhdl.generator.Not;
import fp.util.vhdl.generator.NumericLiteral;
import fp.util.vhdl.generator.ProcessStatement;
import fp.util.vhdl.generator.Signal;
import fp.util.vhdl.generator.SignalAssignment;
import fp.util.vhdl.generator.SimpleName;
import fp.util.vhdl.generator.StringLiteral;
import fp.util.vhdl.generator.SubType;
import fp.util.vhdl.generator.Use;
import fp.util.vhdl.generator.Waveform;
import fp.util.vhdl.generator.WaitStatement;


public class VHDLCircuit extends Circuit {

  private Object _tech_object;

  //'just one ??
  private static DesignFile _design_file;
  //private static VHDLInit _init;
  private static HashMap _vhdl_libs;

  private DesignUnit _design_unit;

  private SimpleName _name;

  private HashMap inputs;
  private HashMap outputs;
  private HashMap widths;

  boolean built = false;

  public VHDLCircuit(Circuit parent, Object tech_object, String name) {
    super(parent, name);

    inputs = new HashMap();
    inputs.put(".reset", new SimpleName("w_reset"));
    inputs.put(".start", new SimpleName("w_start"));
    outputs = new HashMap();
    outputs.put(".done", new SimpleName("w_o_done"));
    widths = new HashMap();

    _tech_object = tech_object;

    if (parent == null) {
      // some init.
      HashSet lib_names = new HashSet();
      _vhdl_libs = new HashMap();
      
      fp.hwdesc.Library lib_conf = GlobalOptions.library;

      lib_names.add(lib_conf.getFileName());
      for (Iterator iter=lib_conf.getRequiredFiles().iterator(); 
	   iter.hasNext(); ) {
	String required_file = (String)iter.next();
	// I don't know what will happen for name collisions here, but
	// it looks like fun!!
	lib_names.add(required_file);
      }
      
      for(Iterator iter=lib_names.iterator(); iter.hasNext(); ) {
	String file_name = (String)iter.next();
	_vhdl_libs.put(file_name, new ParseModule(file_name));

      }
    }

  }

  public SimpleName getVHDLName() {
    if (_name == null) {
      _name = new SimpleName(getRefName());
    }
    return _name;
  }

  DesignUnit getVHDLParent() { return _design_unit; }

  DesignFile getDesignFile() { return _design_file; }


  public boolean setWidth() {
    // What is this for???
    return true;
  }

  /*
    
  So the 40,000 dollar question of the day is, do I merge the modules
  here or do I wait?  I think I merge them all together.

  */

  HashMap getModules() { 
    HashMap result = new HashMap();
    for(Iterator iter=_vhdl_libs.values().iterator(); iter.hasNext(); ) {
      //VHDLInit init = (VHDLInit)iter.next();
      ParseModule init = (ParseModule)iter.next();

      HashMap map = init.getModules();
      // sanity check
      for(Iterator map_iter=map.keySet().iterator(); map_iter.hasNext(); ) {
	String name = (String)map_iter.next();
	if (result.containsKey(name)) {
	  System.out.println("Collision in the mapping of VHDL modules");
	  System.out.println(" colliding name "+name);
	  System.out.println(" I will still merge, but you may not get what "
			     + "is desired.");
	  
	}
      }
      result.putAll(map);
    }    

    return result;
  }

  protected Circuit newCircuit(Circuit graph, String name) {
    return new VHDLCircuit(graph, _tech_object, name);
  }

  protected Constant newConstant(Circuit graph, String name,
				 String value, int width, int type) {
    return new VHDLConstant(graph, name, value, width, type);
  }

  protected FSM newFSM(Circuit graph, String name, StateMachine transitions) {
    return new VHDLFSM(graph, name, transitions);
  }

  protected Memory newMemory(Circuit graph, String name, 
			     int width, int a_width, 
			     int[] contents) {
    return new VHDLMemory(graph, name, width, a_width, contents);
  }

  protected Net newNet(Circuit graph, String name) {
    return new VHDLNet(graph, name);
  }
  
  protected Node newNode(Circuit graph, String name, HashMap ports, 
			 String object, Object[] objects) {
    return new VHDLNode(graph, name, ports, object, objects);
  }
  
  protected Operator newOperator(Circuit graph, String name, 
				 Operation type) {
    return new VHDLOperator(graph, name, type);
  }

  protected Port newPort(Circuit graph, String name, int width, 
			 int direction) {
    return new VHDLPort(graph, name, width, direction);
  }

  protected Register newRegister(Circuit graph, String name, int width, 
				 String contents) {
    return new VHDLRegister(graph, name, width, contents);
  }


  void buildInstance(Circuit c) {
    DesignUnit du = ((VHDLCircuit)c.getParent()).getVHDLParent();
    LibraryUnit lu = du.getLibraryUnit();
      //Entity e = lu.getEntity();

    Architecture a = lu.getArchitecture();
    
    // get name ?? -- this is supposed to be a "class" name 
    Component comp = addComponent(a, c);
    
    Instance inst = new Instance(new SimpleName(c.getName()), comp);
    for (Iterator iter=c.getPorts().iterator(); iter.hasNext();) {
      Port p = (Port)iter.next();
      
      // maps "port" -> "signal"
      HashSet infos = null;
      if (p.getDirection() == PortTag.IN) {
	infos = p.getInPorts();
      } else if (p.getDirection() == PortTag.OUT) {
	infos = p.getOutPorts();
      } else {
	System.out.println(" VHDLCircuit: buildInstance(): This is complicated  -- fix me.");
	System.exit(-1);
      }
      
      // This is tricky VHDL does not allow multiple wires with different names.  They
      // must be explicity the same name or merged at some point.
      Iterator info_iter = infos.iterator(); 
      // okay we will test ...
      if (info_iter.hasNext()) {
	PortTag first = (PortTag)info_iter.next();

	inst.addPortMap(new SimpleName(((VHDLPort)p).getIdentifier()),
			((VHDLNet)first.getNet()).getVHDLName());
      }
    }
    a.addStatement(inst);
    
  }

  
  void addLibraries(DesignUnit du) {
    // this should really check to see or somehow
    // libs need to be added for modules.
    du.addLibrary("ieee");
    du.addUse(new Use("ieee.std_logic_1164.all"));
    du.addUse(new Use("ieee.std_logic_unsigned.all"));
    du.addUse(new Use("ieee.std_logic_arith.all"));
  }


  Component addComponent(Architecture a, Circuit c) {
    Component comp = new Component(((VHDLCircuit)c).getVHDLName());
    for (Iterator iter=c.getPorts().iterator(); iter.hasNext();) {
      Port p = (Port)iter.next();
      comp.addPort(((VHDLPort)p).getVHDLPort());
    }
    a.addItem(comp);
    return comp;
  }


  public void build(String name, Object[] objs) {
    // if top insert top stuff and libraries
    // add a design thinger -- the design unit <--> Level of heirachy.
    //   -- for the design unit add ports to the entity
    //   -- add the architecture
    //       -- add signals
    //       -- add everything else (in progress.)
    
    //System.out.println("TODO build() " + getRefName());
    // crazy
    if (built) return;
    
    if (getParent() == null) {
      _design_file = new DesignFile();
      _design_unit = new DesignUnit(getName());

      DesignUnit du = _design_unit;
      _design_file.addDesignUnit(du);

      addLibraries(du);

    } else {
      /*
	If I am not the top, I think I have two jobs.  -- No I do not
	think that is right.  The circuit that wants the instatiations
	should build them itself.  A circuit is responsible for the
	leaves and appearence those things in it.
      */

      buildInstance(this);

      _design_unit = new DesignUnit(getRefName());
      
      DesignUnit du = _design_unit;
      // how do I get in the file ???
      getDesignFile().addDesignUnit(du);

      addLibraries(du);
      
    }   

    // signals ??
    //System.out.println("Build Nets");
    no_net:
    for(Iterator iter = getNets().iterator(); iter.hasNext(); ) {
      VHDLNet net = (VHDLNet)iter.next();
      // need to see if net exists in portmap

      /*
	Just checking sources is not sufficent -- this can happen
	to Port->Sink Source->Port and also to FSM and probably
	black boxes (which are nodes -- upgraded to Circuits (maybe)).

	OKay -- maybe I should change the port hashset to a hashmap
	so I can quickly find the names....  This should work for everything
	now, but it could be costly.

      */

      for(Iterator port_iter = getPorts().iterator(); port_iter.hasNext(); ) {
	Port port = (Port)port_iter.next();
	
	if (port.getRefName().equals(net.getName())) {
	  // skip building this net ??
	  //System.out.println(" Not adding signal "+net);
	  continue no_net;
	}
      }
      net.build(name, objs);
    }

    //System.out.println("Build Nodes");
    // ports -- but does the order matter ... no, not for concurrent statements.
    for(Iterator iter = getNodes().iterator(); iter.hasNext(); ) {
      Node node = (Node)iter.next();
      node.build(name,objs);
    }

    //System.out.println("Build SubCircuits");
    for(Iterator iter = getCircuits().iterator(); iter.hasNext(); ) {
      Circuit c = (Circuit)iter.next();

      c.build(name,objs);
    }


    if (getParent() == null) {
      // we need to get just the file basename and path from it
      int index = name.lastIndexOf(System.getProperty("file.separator"));
      int last_dot = name.lastIndexOf(".");
      String basename = name.substring(index+1,last_dot);
      String path = name.substring(0, index+1);

      // now create the changed file name
      String file_name = path + "" + basename + ".vhd";

      DesignFile.write(_design_file, file_name);

      // we should hack in a test bench generator to ease
      // making testbenches for our stuff.
      
      if (GlobalOptions.makeTestBench)
	makeTestBench(name, this);
    }