aa_fplib.dat

一种将c高级语言转化给VHDL的编译器

;LA-CC 05-135 Trident 0.7.1
;
;Copyright Notice
;Copyright 2006 (c) the Regents of the University of California.
;
;This Software was produced under a U.S. Government contract 
;(W-7405-ENG-36) by Los Alamos National Laboratory, which is operated by 
;the University of California for the U.S. Department of Energy. The U.S. 
;Government is licensed to use, reproduce, and distribute this Software. 
;Permission is granted to the public to copy and use this Software without 
;charge, provided that this Notice and any statement of authorship are 
;reproduced on all copies. Neither the Government nor the University makes 
;any warranty, express or implied, or assumes any liability or 
;responsibility for the user of this Software.


(library fplib
  (libname aa)
  (libinclude fplib.pkg_fplib_ieee.all)  

  (libobject IEEEAdd_clk aa_fpadd
    (generic wE (integer 8))
    (generic wF (integer 23))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port in 
      (name nB) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nB in1)
    (map nR out)
    (gmap wE 8)
    (gmap wF 23)
  )

  (libobject IEEEAdd_clk aa_dpadd
    (generic wE (integer 11))
    (generic wF (integer 52))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port in 
      (name nB) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nB in1)
    (map nR out)
    (gmap wE 11)
    (gmap wF 52)
  )

  (libobject IEEEsub_clk aa_fpsub
    (generic wE (integer 8))
    (generic wF (integer 23))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port in 
      (name nB) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nB in1)
    (map nR out)
    (gmap wE 8)
    (gmap wF 23)
  )

  (libobject IEEEsub_clk aa_dpsub
    (generic wE (integer 11))
    (generic wF (integer 52))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port in 
      (name nB) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nB in1)
    (map nR out)
    (gmap wE 11)
    (gmap wF 52)
  )

  (libobject IEEEmul_clk aa_fpmul
    (generic wE (integer 8))
    (generic wF (integer 23))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port in 
      (name nB) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nB in1)
    (map nR out)
    (gmap wE 8)
    (gmap wF 23)
  )

  (libobject IEEEmul_clk aa_dpmul
    (generic wE (integer 11))
    (generic wF (integer 52))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port in 
      (name nB) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nB in1)
    (map nR out)
    (gmap wE 11)
    (gmap wF 52)
  )

  (libobject IEEEdiv_clk aa_fpdiv
    (generic wE (integer 8))
    (generic wF (integer 23))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port in 
      (name nB) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nB in1)
    (map rR out)
    (gmap wE 8)
    (gmap wF 23)
  )
      
  (libobject IEEEdiv_clk aa_dpdiv
    (generic wE (integer 11))
    (generic wF (integer 52))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port in 
      (name nB) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nB in1)
    (map nR out)
    (gmap wE 11)
    (gmap wF 52)
  )
      
  (libobject IEEEsqrt_clk aa_fpsqrt
    (generic wE (integer 8))
    (generic wF (integer 23))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nR out)
    (gmap wE 8)
    (gmap wF 23)
  )

  (libobject IEEEsqrt_clk aa_dpsqrt
    (generic wE (integer 11))
    (generic wF (integer 52))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map clk clk)
    (map nA in0)
    (map nR out)
    (gmap wE 11)
    (gmap wF 52)
  )

  (libobject IEEEinv aa_fpinv
    (generic wE (integer 8))
    (generic wF (integer 23))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map a in0)
    (map q out)
    (gmap wE 8)
    (gmap wF 23)
  )

  (libobject IEEEinv aa_dpinv
    (generic wE (integer 11))
    (generic wF (integer 52))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map nA in0)
    (map nR out)
    (gmap wE 11)
    (gmap wF 52)
  )

  (libobject IEEEabs aa_fpabs
    (generic wE (integer 8))
    (generic wF (integer 23))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map nA in0)
    (map nR out)
    (gmap wE 8)
    (gmap wF 23)
  )

  (libobject IEEEabs aa_dpabs
    (generic wE (integer 11))
    (generic wF (integer 52))
    (port in 
      (name nA) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (port out 
      (name nR) 
      (type std_logic) 
      (size (wF wE 1 + +)))
    (map nA in0)
    (map nR out)
    (gmap wE 11)
    (gmap wF 52)
  )

)