quixilica.dat

一种将c高级语言转化给VHDL的编译器

;LA-CC 05-135 Trident 0.7.1
;
;Copyright Notice
;Copyright 2006 (c) the Regents of the University of California.
;
;This Software was produced under a U.S. Government contract 
;(W-7405-ENG-36) by Los Alamos National Laboratory, which is operated by 
;the University of California for the U.S. Department of Energy. The U.S. 
;Government is licensed to use, reproduce, and distribute this Software. 
;Permission is granted to the public to copy and use this Software without 
;charge, provided that this Notice and any statement of authorship are 
;reproduced on all copies. Neither the Government nor the University makes 
;any warranty, express or implied, or assumes any liability or 
;responsibility for the user of this Software.


(library Quixilica 
  (libname qx)
  (libinclude Quixilica.qxFpComponents.all)  
  (libobject fpadd qx_fpadd
    (generic ew (integer 8))
    (generic mw (integer 24))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name b) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name bInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name s) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map b in1)
    (map aInv 0)
    (map bInv 0)
    (map s out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 8)
    (gmap mw 24)
  )

  (libobject fpadd qx_dpadd
    (generic ew (integer 11))
    (generic mw (integer 53))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name b) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name bInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name s) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map b in1)
    (map aInv 0)
    (map bInv 0)
    (map s out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 11)
    (gmap mw 53)
  )

  (libobject fpadd qx_fpsub
    (generic ew (integer 8))
    (generic mw (integer 24))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name b) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name bInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name s) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map b in1)
    (map aInv 0)
    (map bInv 1)
    (map s out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 8)
    (gmap mw 24)
  )

  (libobject fpadd qx_dpsub
    (generic ew (integer 11))
    (generic mw (integer 53))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name b) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name bInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name s) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map b in1)
    (map aInv 0)
    (map bInv 1)
    (map s out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 11)
    (gmap mw 53)
  )

  (libobject fpmul qx_fpmul_soft
    (generic ew (integer 8))
    (generic mw (integer 24))
    (generic embedded (boolean false))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name b) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name bInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name p) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map b in1)
    (map aInv 0)
    (map bInv 0)
    (map p out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 8)
    (gmap mw 24)
    (gmap embedded false)
  )

  (libobject fpmul qx_dpmul_soft
    (generic ew (integer 11))
    (generic mw (integer 53))
    (generic embedded (boolean false))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name b) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name bInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name p) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map b in1)
    (map aInv 0)
    (map bInv 0)
    (map p out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 11)
    (gmap mw 53)
    (gmap embedded false)
  )

  (libobject fpmul qx_fpmul_hard
    (generic ew (integer 8))
    (generic mw (integer 24))
    (generic embedded (boolean false))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name b) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name bInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name p) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map b in1)
    (map aInv 0)
    (map bInv 0)
    (map p out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 8)
    (gmap mw 24)
    (gmap embedded true)
  )

  (libobject fpmul qx_dpmul_hard
    (generic ew (integer 11))
    (generic mw (integer 53))
    (generic embedded (boolean false))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name b) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name bInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name p) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map b in1)
    (map aInv 0)
    (map bInv 0)
    (map p out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 11)
    (gmap mw 53)
    (gmap embedded true)
  )

  (libobject fpdiv qx_fpdiv
    (generic ew (integer 8))
    (generic mw (integer 24))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name n) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name d) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name nInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name dInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name q) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name divByZero) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map n in0)
    (map d in1)
    (map nInv 0)
    (map dInv 0)
    (map q out)
    (map invalidOp open)
    (map divByZero open)
    (map overflow open)
    (map underflow open)
    (gmap ew 8)
    (gmap mw 24)
  )
      
  (libobject fpdiv qx_dpdiv
    (generic ew (integer 11))
    (generic mw (integer 53))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name n) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name d) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name nInv) 
      (type std_logic) 
      (size 1))
    (port in 
      (name dInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name q) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name divByZero) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map n in0)
    (map d in1)
    (map nInv 0)
    (map dInv 0)
    (map q out)
    (map invalidOp open)
    (map divByZero open)
    (map overflow open)
    (map underflow open)
    (gmap ew 11)
    (gmap mw 53)
  )
      
  (libobject fpsqrt qx_fpsqrt
    (generic ew (integer 8))
    (generic mw (integer 24))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name q) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map aInv 0)
    (map q out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 8)
    (gmap mw 24)
  )

  (libobject fpsqrt qx_dpsqrt
    (generic ew (integer 11))
    (generic mw (integer 53))
    (port in 
      (name clk) 
      (type std_logic) 
      (size 1))
    (port in 
      (name a) 
      (type std_logic) 
      (size (mw ew +)))
    (port in 
      (name aInv) 
      (type std_logic) 
      (size 1))
    (port out 
      (name q) 
      (type std_logic) 
      (size (mw ew +)))
    (port out 
      (name invalidOp) 
      (type std_logic) 
      (size 1))
    (port out 
      (name overflow) 
      (type std_logic) 
      (size 1))
    (port out 
      (name underflow) 
      (type std_logic) 
      (size 1))
    (map clk clk)
    (map a in0)
    (map aInv 0)
    (map q out)
    (map invalidOp open)
    (map overflow open)
    (map underflow open)
    (gmap ew 11)
    (gmap mw 53)
  )

)