xd1_inter.dat

一种将c高级语言转化给VHDL的编译器

;LA-CC 05-135 Trident 0.7.1
;
;Copyright Notice
;Copyright 2006 (c) the Regents of the University of California.
;
;This Software was produced under a U.S. Government contract 
;(W-7405-ENG-36) by Los Alamos National Laboratory, which is operated by 
;the University of California for the U.S. Department of Energy. The U.S. 
;Government is licensed to use, reproduce, and distribute this Software. 
;Permission is granted to the public to copy and use this Software without 
;charge, provided that this Notice and any statement of authorship are 
;reproduced on all copies. Neither the Government nor the University makes 
;any warranty, express or implied, or assumes any liability or 
;responsibility for the user of this Software.


(library xd1
  (libname work)
  (libinclude work.all)

  (libobject xd1_top xd1_top
     (port in
	(name clk)
	(type std_logic)
	(size 1))
     (port in
	(name reset_n)
	(type std_logic)
	(size 1))
     (port in
	(name i_data)
	(type std_logic)
	(size 64))
     (port in
	(name i_addr)
	(type std_logic)
	(size 22))
     (port in 
        (name i_status)
	(type std_logic)
	(size 4))
     (port out
	(name o_reg)
	(type std_logic)
	(size 64))
     (port out
	(name o_mem)
	(type std_logic)
	(size 64))
     (port out
	(name o_bmem)
	(type std_logic)
	(size 64))

     (for x in (0 1 2 3)
     	(port in
	   (name mem$x_dr)
	   (tag mem$x)
	   (type std_logic)
	   (size 64)
	   (open low))
	(port out
	   (name mem$x_ar)
	   (tag mem$x)
	   (type std_logic)
	   (size 20)
           (open low))
        (port out
           (name mem$x_re_n)
           (tag mem$x)
           (type std_logic)
           (size 1)
           (open high))
        (port out
           (name mem$x_dw)
           (tag mem$x)
           (type std_logic)
           (size 64))
        (port out
           (name mem$x_aw)
           (tag mem$x)
           (type std_logic)
           (size 20)
           (open low))
        (port out
           (name mem$x_we_n)
           (tag mem$x)
	   (type std_logic)
           (size 1)
           (open high))

	(map mem$x_dr mem$x_dr)
	(map mem$x_ar mem$x_ar)
	(map mem$x_re_n mem$x_re_n)
	(map mem$x_dw mem$x_dw)
	(map mem$x_aw mem$x_aw)
	(map mem$x_we_n mem$x_we_n)
      )
	
      (map clk clk)
      (map reset_n reset_n)
      (map i_data i_data)
      (map i_addr i_addr)
      (map i_status i_status)
      (map o_reg o_reg)
      (map o_mem o_mem)
      (map o_bmem o_bmem)
  )	
)